6061 - CrossLink: Do we have layout recommendation and break out examples for the ckfBGA in FPGA-TN-02024?
In section 4.8 of FPGA-TN-02024, This breakout uses a LIF-MD6000 PLD in a 6.5 mm x 6.5 mm and 7.0 mm x 7.0 mm, and so on. The first is for ctfBGA while the latter is ckfBGA.
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5224 - CrossLink: How to use SPI and CDONE pins for general-purpose I/O (GPIO)?
To use SPI pins as general-purpose I/O (GPIO), disable the port option for both "Slave SPI Port" and "Master SPI Port" on the Global Preferences tab in the Spreadsheet View tool of Diamond. To use the CDONE pin as GPIO, set CDONE PORT as "CDONE_PORT ...
932 - Diamond: Where can I find RTL coding examples?
Diamond: There are a number of coding examples for Lattice devices included with the Diamond. From the Diamond Project Navigator go to the pull down menu File -> Open example, select the family and the source code entry of interest.
6819 - Lattice Diamond: How do i generate the pin layout files in Diamond?
You can generate the pinout file for the desired device through the diamond SW. Please follow the steps below: 1) Open Spread Sheet View 2) Once Opened, Export the Pin Layout file through “File”, as Shown below: 3) Select the details that you will be ...
2378 - Diamond: In Lattice Diamond, what is the difference between a Pin Layout File and a Pin Out file?
A Pin Layout File is a report of pin information and assignments in your design. It is created from within the Lattice Diamond Spreadsheet View using File>Export Pin Layout File The Pin Layout File can be a list of available pins, pad names, ...
5229 - CrossLink / DPHY to CMOS IP v1.2: Why am I not able to place the GPIO/IO_ports on bank0 in CrossLink while using DPHY to CMOS IP?
Description: When placing CMOS IO to Bank0, P&R errors are encountered indicating of wrong placement in the I/O bank0. Solution: In CrossLink, IP has been updated by adding ODDR hard block at the output side to enhance the design to support more than ...