5229 - CrossLink / DPHY to CMOS IP v1.2: Why am I not able to place the GPIO/IO_ports on bank0 in CrossLink while using DPHY to CMOS IP?

• Related Articles

• 5224 - CrossLink: How to use SPI and CDONE pins for general-purpose I/O (GPIO)?

  To use SPI pins as general-purpose I/O (GPIO), disable the port option for both "Slave SPI Port" and "Master SPI Port" on the Global Preferences tab in the Spreadsheet View tool of Diamond. To use the CDONE pin as GPIO, set CDONE PORT as "CDONE_PORT ...

• 7242 - Radiant versions 2023.1 and newer: Why is there a MAP DRC update on 2023.1 and newer versions of Radiant that blocks the compilation of designs with all configuration ports disabled?

  In the Nexus series of devices, if you intend to utilize JTAG ports as GPIO by de-asserting JTAG_EN, then there must be another dual-use pin (e.g. I2C) that remains in “persisted” mode (e.g. I2C must stay as I2C and not become a GPIO). Keeping I2C ...

• 2666 - MachXO2: Datasheet states that LVDS33 is supported, but why user cannot select this IO Type in the software and an error is generated if it is added manually to the .lpf file ?

  Within the MachXO2 device, the settings for LVDS25 and LVDS33 are identical, the only difference is the voltage level applied to VCCIO. So to implement the IO's as LVDS33 in Lattice Diamond the IO's are set to LVDS25. The user then needs only apply ...

• 6603 - Radiant: How to perform IP re-generation using ipgen?

  First, run "ipgen.exe -h" from the tcl console to view all the command options as shown below. usage: ipgen.exe [-h] [-o OUTPUT_DIR] [-proj_dir PROJ_DIR] -ip IP_MODULE_DIR [-cfg IP_CONFIG_FILE] [-skip_uniquify SKIP_UNIQUIFY_HDL] [-cfg_value ...

• 6994 - Lattice Radiant: How do I use the RGB pins on iCE40UltraPlus as GPIO?

  The SB_IO_OD primitive is only available for the iCECube2 SW, you will have to use BB_OD as this is the equivalent primitive for the opendrain buffer in Radiant. Note that for Radiant, BB_OD is automatically mapped in the netlist/design whenever you ...