5229 - CrossLink / DPHY to CMOS IP v1.2: Why am I not able to place the GPIO/IO_ports on bank0 in CrossLink while using DPHY to CMOS IP?
Description:
When placing CMOS IO to Bank0, P&R errors are encountered indicating of wrong placement in the I/O bank0.
Solution:
In CrossLink, IP has been updated by adding ODDR hard block at the output side to enhance the design to support more than 150 MHz pixel clock and ODDR is not available in the bank0. The user should assign/place outputs of IP in either bank1 or bank2 only.
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