Why there are designs passing on MAP showing a good SLICE utilization percentage but failing PAR showing unplaced SLICEs due to 100% SLICE utilization percentage?
To give a background on this, in a single SLICE, there can be two possible registers/FFs. Map does the SLICE utilization calculation solely based on the number of registers/FF per SLICE. Architecturally, there are 2 FFs/registers and 2 LUTs per SLICE, and then 4 SLICEs per PFU.
For PAR, it is a different story as there are PLC rules being considered before placing two registers together in a single SLICE.
In a nutshell, registers can be placed on a SLICE based if there clock enable (CE), clock input (CLKIN), and local set/reset (LSR) signals are common. If two registers do not have the same or common signals on all of this, then the registers are placed on separate SLICEs.
Image from Datasheet