1289 - Lattice ispLEVER: Place and Route: Why do I get a warning message about an edge clock not on a sweet site during place and route when targeting an SC/M?

1289 - Lattice ispLEVER: Place and Route: Why do I get a warning message about an edge clock not on a sweet site during place and route when targeting an SC/M?

Lattice ispLEVER: Place and Route: In congested designs a conflict may occur resulting in an unroutable condition in PAR. This may be due to user constraints or unfavorable placement of logic by the software. Depending on the size and complexity of a design, it may become necessary to specify the locations of the PLL's, DLL's, and CLKDIV's to properly utilize the Edge clock and Primary clock routing for optimal performance and routability. Another consequence in these types of designs is getting an error or warning message during place and route stating that a primary or edge clock cannot be accessed, resulting in a general route being used to put the clock back onto the primary or edge routing.

The following is an example of an edge clock conflict. You have a PLL using the CLKOP and a receive clock driving a CLKDIV. The user constraints (or the place and route process can place) the PLL at PLL_ULCB, and the receive clock is placed such that it drives CLKDIV7D. In this case, PAR will warn the user (so long as the other edge clocks are not used) that one of these clocks is diverted to general routing in order to get around this conflict. The reason for this conflict can be seen in TN1098, Figure 33. There is an arrow indicating the input clock is driving this edge as well as the PLL being on this edge. Figure 9 also gives a textual representation of how these connections are made. The following is an example of this warning:

WARNING - par: edge clock /rdclk driver is PIO/IOL but not
placed on sweet site or edge clock branch is occupied, will be
routed using generic routing to the branch and may suffer from
excessive delay or skew.

In TN1098, Figure 33 and Table 10 provide insight into the SC/M clock.
http://www.latticesemi.com/documents/tn1098.pdf
The figure shows the available edge clocks and their drivers. The table lists the available primary clocks and their drivers. In most cases, you can change the PLL output (CLKOS to CLKOP, or vise versa) or the PLL location in order to work around an existing pinout. In more congested designs, it may be necessary to drive a PLL output to a DLL in order to change the edge clock route in the design. The possible configurations of PLLs to DLLs are given in the PLL/DLL cascading section of TN1098. An example of PLL, DLL, and CLKDIV placement is as follows.
LOCATE COMP "" SITE "PLL_LLCB" ;
LOCATE COMP "" SITE "DLL_LRCC" ;
LOCATE COMP "" SITE "CLKDIV7A" ;

We suggest preferencing primary clocks. Generally, the tools will automatically promote these and other clocks as necessary. In a congested design it may become necessary to preference the clocks into quadrants. The tools will error out if a clock is unroutable. An example of constrainting clocks to specific quadrants is as follows.
USE PRIMARY NET "clk1" QUADRANT_BL QUADRANT_BR ;
USE PRIMARY NET "clk2" QUADRANT_TL QUADRANT_TR ;