2831 - Lattice Diamond / ECP3: Why is software unable to complete PAR on the LVDS clock when utilizing general routing?
Description:An error message is received when routing with general routingERROR - par: netsanitycheck: the clock clk_lvds_rx_p_c on comp adcif_inst/Inst3_EHXPLLF port CLKI is driven by general routing through comp clk_lvds_rx_p. Please consult Lattice technical support for the appropriate constraints when using general routing for clocks.
ERROR - par: Errors found, PAR will exit now.
Exiting par with exit code 19
Exiting mpartrce with exit code 19
Done: error code 19
Solution:The CLKI of the PLL must be driven with a primary clock net rather then general clock routing.
The issue is due to the input clock routing directly to both CLKDIV and PLL primitives. This causes the router to get confused and use general routing instead of the dedicated path.
Add the following workaround to your *.lpf file:
USE PRIMARY NET “clk_lvds_rx_p_c”;
User can also refer to FPGA-TN-02191 - LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide section PLL Inputs and Outputs for more information.
ECP3 webpage: https://www.latticesemi.com/en/Products/FPGAandCPLD/LatticeECP3
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