2612 - Why is some logic in a sub-module not packed into the group after Place and Route (PAR) when this sub-module is grouped with the HGROUP attribute in the source code?
Sometimes, Synplify will move some logic out of the sub-module for the optimization purpose by default. In order to avoid it, the syn_hier attribute should be added in the sub-module.
The usage example is shown below:
In Verilog,
module dp(clk, rst, din, dout) /* synthesis syn_hier = "fixed" */;
In VHDL,
architecture struct of dp is
attribute syn_hier : string;
attribute syn_hier of struct: architecture is "fixed";
When syn_hier is set as "fixed", it prevents all optimizations performed across hierarchical boundaries and retains the port interfaces as well. Then all logic in the sub-module will be placed together in a group during PAR.
Please refer to Lattice Attribute section and Directive Summary of Synplify Pro's help.