SED / SEC
5304 - All Devices: Can we access any NON-JTAG port (Wishbone, I2C, SPI or CPU) while SED is running in user mode?
No. While the SED is running if the user tries to access the device using any non-jtag port (like WB, I2C, SPI or CPU) the SED will be terminated.
3964 - SED: How to run Soft Error Detect (SED) block when the user logic is running in LatticeXP2 devices?
Description: This article describe the ideal way of using SED block in LatticeXP2 product. Solution: According to LatticeXP2 Product Change Notification (PCN)# 02B-12, the SED block cannot be run during normal active operation. However, the SED ...
2320 - Why do my BSCAN2 outputs change state randomly?
Solution: Lattice provides the BSCAN2 Intellectual Property as a pre-compiled NGO file that can be inserted into your own designs. The early BSCAN2 NGO files included an instantiation of the Global Set/Reset (GSR) macro. Explicit instantiation of the ...
1806 - Are programming and configuring a Programmable Logic Device two different processes?
The meaning of these two terms depends on the programmable logic device (PLD) used. Lattice provides three kinds of technologies in the PLD products you purchase. The technologies are: EEPROM based: 4000 family of CPLD's SRAM based: ECP2, ECP3, ECP4 ...
1766 - LatticeECP3: Is the LatticeECP3 SCM(Serial Configuration Mode) similar to LatticeECP2 slave serial programming mode?
Yes, the LatticeECP2 slave serial programming mode and the LatticeECP3 SCM modes are identical. Both modes use a simple 2-pin interface(CCLK and DIN). The details of these programming modes are described in the LatticeECP3 sysCONFIG Usage guide and ...
7171 - All Nexus: Unable to re-program Nexus devices more than once without power cycling the device. At DCE, bank VCCIO is set to "AUTO"
Description: In the Device Constraint Editor, it is recommended that the actual voltage must be reflected on VCCIO/CONFIGIO banks. The default "AUTO" in VCCIO Bank setting is equivalent to 3.3V, and CONFIGIO_VOLTAGE_BANK0/1 = NOT_SPECIFIED If actual ...
1705 - What is the start point of “input operation” and the start point of “output operation” after TransFR command in “Leave Alone” I/O State?
The use of the TransFR command is discussed in more detail in TN1087, Minimizing System Interruption During Configuration Using TransFR Technology. This tech note is available from the Lattice web site at the following web link: ...
6395 - All Nexus: What is the default state of Nexus Platform's sysCONFIG pins?
Table below provides tabulated information regarding the default state of all sysCONFIG pins. User may refer to FPGA-TN-02099 for more information.
7366 - All Nexus: Why does the SEI tool generate frame error locations that exceed the expected total number of frames shown in Table 7.1 of the “Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform [FPGA-TN-02076-1.9]” document?
The address counter or frame number for each frame does not line up linearly. There is a gap when assigning a frame number for each frame, and therefore the data frame number reported in the SEI editor is expected and can be larger than the ...
7357 - All Nexus: What are the input and output signals timing sensitivity of SEDC IP?
All SEDC input signals will be accepted asynchronously since they will be synced automatically by the SEDC IP internal synchronizer, while SEDC output signals will be synchronous with the input clock (cfg_clk_o of the internal oscillator).
7340 - Could the IO design be changed between two bitstreams when performing TransFR?
A fundamental rule for TransFR, there should be no IO design change (add, remove, alter the IO standard or alter IO direction) between the two bitstreams before and after the TransFR, because the purpose of TransFR is to hold the IO standard and ...
7110 - SEDC: Why does errcrc_o asserts when a correctable error is detected?
The sedc_errcrc_o normally asserts when there is a soft-error detected. It will transition from high to low in the second run if the single-bit soft-error is correctable. To support this, the user has to monitor the 2 clock cycle low pulse of BUSY ...
2125 - What is the device programming time of a Lattice FPGA?
Solution: The time to program a Lattice FPGA is dependent on several factors including configuration mode, programming speed, and device size. Some configuration modes and methods are faster than others. The complete configuration time inherently ...
6291 - CertusPro-NX: Can we use SED/SEC with “sedc_cof_i = 1” for production?
Definition: Yes, the set sedc_cof_i can be set to high or 1 for production. In this manner, the SED/SEC flow will continue to the next frame even error has been detected. In the scenario that sedc_cof_i is low, it will stop SED/SEC when ...
6764 - MachXO3: How to perform OTP programming in MachXO3?
See below steps: 1. In the Lattice Diamond Software - Spreadsheet View, Global Preferences in Diamond Tool, set the OTP column as ONE_TIME_PROGRAM = FLASH, then generate the .JED file. 2. Create an .XCF file from Diamond Programmer using the .JED ...
7063 - Radiant 2023.1 and SEDC: How to use SEDC properly with reveal?
Description: When observed at Reveal for CrossLink-NX using SoftJTAG, a timing error occurs. Solution: When using reveal with SEDC make sure that no distributed RAM is used for both Trace Signal Setup and Trigger Signal Setup like below:
7041 - Diamond 3.9 and All MachXO: Why here is no simulation model for SEDFA/SEDFB Primitive with its support devices?
Description: After installing Diamond, I find under "xxxx\cae_library\simulation", there not have a simulation model for XO3L SEDFA/SEDFB Primitive. Look into this, I find XO2 device also not have a simulation model for SEDFA/SEDFB Primitive. ...
2681 - MachXO2: What happens to the internal oscillator during background flash programming?
The internal oscillator of the MachXO2 remains active to the user logic during transparent configuration. The clock provided by the internal oscillator to the fabric will not stop or be influenced while the oscillator is also being used internally ...
2665 - MACHXO2: Are the registers initialized to a known value after a re-configuration operation?
In MachXO2, during normal device power-up, all registers are initialized to zero. The same is true for re-configuration operations. After re-configuration (e.g. 'REFRESH' command or PROGRAMN pin toggle) the MachXO2 device performs the same ...
452 - LatticeXP2: Why doesn't the USERCODE assigned using Spreadsheet View match the value retrieved from a LatticeXP2 programmed with an encrypted bitstream?
The program that creates the FPGA bit stream encrypts the USERCODE in addition to the data used to configure the LatticeXP2. After the LatticeXP2 FPGA is programmed the USERCODE can be retrieved from the LaticeXP2. The value is available from either ...
6637 - ECP5 Family: How to setup a SysConfig Daisy Chain in Lattice ECP5 or ECP5-5G?
To setup the SysConfig Daisy Chain using Bypass option, the following requirements and steps should be followed:
6584 - CertusPro-NX: Does sedc_err_o and sedc_errm_o implementation of 'sticky' functionality in the Silicon itself or in some soft logic?
Description:sedc_err_o and sedc_errm_o are implemented with "sticky" functionality. "Sticky" functionality is defined as functionality where in the setting persist even through reset. The implementation of sticky bit is implemented in Silicon.
6583 - All Nexus: For Nexus SED/SEC, is 1-bit of error always correctable?
Any single bit error can be corrected by hardware. If for some reason the bit becomes permanently stuck then it would fail the verification step after correction. Every time the hardware does error correction it verifies first the correction before ...
6582 - All Nexus: Referring to SED/SEC User Guide for Nexus Platform (FPGA-TN-02076):In ‘Frame n’, there is significant latency between sedc_errc_o asserting and sedc_err_o asserting. What is causing this latency?
Once an error is detected, the latency basically implies that the hardware goes into error search mode to find the type and location of the error so it can be corrected.
6207 - CertusPro-NX: How to inject a soft error using Radiant?
To inject an error: (1) No need to disable SEDC. (2) Compile the design from Synthesis to PAR. Note: Do not export bitstream yet. (3) Go to Tools>SEI Editor then enable the SEI. (4) Generate SEI bitstream from Radiant's Export Files. (5) Program the ...
6574 - MachXO2/MachXO3: Why is the IO state locked during TransFR Operation of MACHXO3 device?
Description: The IO electrical properties like Drive strength, Slew, Open-Drain, and Pullmodes are preserved (carried over) from the initial configuration. These settings are not cleared unless the device is Power-cycled or loaded with a new ...
6548 - Why does the change in the Feature Row appear to take effect immediately when using a background mode operation?
The Feature Row programming will take effect immediately, whether it's Transparent Programming or Normal (offline) Programming. The idea behind it is that we want to make the content inside the shadow register always in sync with the actual flash ...
6970 - MachXO2/MachXO3: Is it possible to turn save power by turning off internal oscillator of MachXO2 and MachXO3?
The internal oscillator of MachXO2 and MachXO3 (OSCH for MachXO2/XO3L/XO3LF and OSCJ for MachXO3D) are turned on by default thus it will consume power even though it is not instantiated in the design. To turn it off at user mode instantiate it at ...
6514 - All Nexus Family: How to set DONE, INTN and PROGRAMN pins as GPIO in Nexus Family?
To use these Configuration pins as an IO, follow the steps below: 1.) The First step is to set this pins to DISABLE (in this case INITN_PORT, DONE_PORT and PROGRAMN_PORT to DISABLE). After running the design flow up to export files, a .fea file will ...
1471 - What happens if the Power goes down during FLASH Programming?
The FLASH Programming flow involves Erase FLASH device,Program, Verify and Secure(optional). A DONE bit will be set once the whole flow is completed. Depending on the point where exactly the power is down, the device behavior changes. 1) If the Power ...
2514 - MachXO2/MachXO3: What is the best way to program a Lattice MachXO2 device in the field with minimum disruption?
Solution: The Lattice MachXO2 devices can be updated in the field by utilizing Lattice's background programming mode and TransFR Technology Background programming: The on-chip flash can be programmed in background mode, while the device and IOs ...
6452 - ECP2/ECP2S: Does ECP2 and ECP2S devices bitstream compatible?
Yes, ECP2 and ECP2S are bitstreams compatible. Therefore the standard Diamond tools may be used for development.