5304 - All Devices: Can we access any NON-JTAG port (Wishbone, I2C, SPI or CPU) while SED is running in user mode?

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• 6179 - How do user program Lattice FPGA after programming a bitstream to the SPI Flash with JTAG_PORT and MASTER_SPI_PORT set to DISABLED?

  Description: When JTAG_PORT and MASTER_SPI_PORT is set to DISABLED, user can no longer access the configuration logic through JTAG and MSPI Port. Thus, user can't perform programming with the interface. Solution: To workaround on this, user can ...

• 3964 - SED: How to run Soft Error Detect (SED) block when the user logic is running in LatticeXP2 devices?

  Description: This article describe the ideal way of using SED block in LatticeXP2 product. Solution: According to LatticeXP2 Product Change Notification (PCN)# 02B-12, the SED block cannot be run during normal active operation. However, the SED ...

• 1409 - How can I access the User Flash Memory(UFM) of MACHXO2 device?<BR>

  You can access the User Flash Memory(UFM) sector via the internal WISHBONE interface of the Embedded Function Block(EFB) module, external Slave SPI port and exteranl I2C Primary port. In addition, you can also access the UFM sector through the JTAG ...

• 1423 - Can I access the on-chip Flash memory use the Master SPI Mode(MSPI) for MACHXO2 device?<br>

  You can not use the Master SPI Mode(MSPI) to access the on-chip Flash memory. This mode is exclusively for SRAM memory configuration. You can use the MSPI port for programming the external SPI Flash device through JTAG mode. This provides a single ...

• 5335 - All FPGA: Does Non-JTAG TransFR support I/O release during TranFR?

  Definition: TransFR (Transparent Field Reconfiguration) is a technology that helps minimize system interruption. This is supported through JTAG and Non-JTAG port (example Wishbone). However, there are some disadvantages of Non-JTAG TransFR. It does ...