7357 - All Nexus: What are the input and output signals timing sensitivity of SEDC IP?

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• 7063 - Radiant 2023.1 and SEDC: How to use SEDC properly with reveal?

  Description: When observed at Reveal for CrossLink-NX using SoftJTAG, a timing error occurs. Solution: When using reveal with SEDC make sure that no distributed RAM is used for both Trace Signal Setup and Trigger Signal Setup like below:

• 6291 - CertusPro-NX: Can we use SED/SEC with “sedc_cof_i = 1” for production?

  Definition: Yes, the set sedc_cof_i can be set to high or 1 for production. In this manner, the SED/SEC flow will continue to the next frame even error has been detected. In the scenario that sedc_cof_i is low, it will stop SED/SEC when ...

• 6584 - CertusPro-NX: Does sedc_err_o and sedc_errm_o implementation of 'sticky' functionality in the Silicon itself or in some soft logic?

  Description:sedc_err_o and sedc_errm_o are implemented with "sticky" functionality. "Sticky" functionality is defined as functionality where in the setting persist even through reset. The implementation of sticky bit is implemented in Silicon.

• 6582 - All Nexus: Referring to SED/SEC User Guide for Nexus Platform (FPGA-TN-02076):In ‘Frame n’, there is significant latency between sedc_errc_o asserting and sedc_err_o asserting. What is causing this latency?

  Once an error is detected, the latency basically implies that the hardware goes into error search mode to find the type and location of the error so it can be corrected.

• 7110 - SEDC: Why does errcrc_o asserts when a correctable error is detected?

  The sedc_errcrc_o normally asserts when there is a soft-error detected. It will transition from high to low in the second run if the single-bit soft-error is correctable. To support this, the user has to monitor the 2 clock cycle low pulse of BUSY ...