6584 - CertusPro-NX: Does sedc_err_o and sedc_errm_o implementation of 'sticky' functionality in the Silicon itself or in some soft logic?

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• 7110 - SEDC: Why does errcrc_o asserts when a correctable error is detected?

  The sedc_errcrc_o normally asserts when there is a soft-error detected. It will transition from high to low in the second run if the single-bit soft-error is correctable. To support this, the user has to monitor the 2 clock cycle low pulse of BUSY ...

• 6291 - CertusPro-NX: Can we use SED/SEC with “sedc_cof_i = 1” for production?

  Definition: Yes, the set sedc_cof_i can be set to high or 1 for production. In this manner, the SED/SEC flow will continue to the next frame even error has been detected. In the scenario that sedc_cof_i is low, it will stop SED/SEC when ...

• 7063 - Radiant 2023.1 and SEDC: How to use SEDC properly with reveal?

  Description: When observed at Reveal for CrossLink-NX using SoftJTAG, a timing error occurs. Solution: When using reveal with SEDC make sure that no distributed RAM is used for both Trace Signal Setup and Trigger Signal Setup like below:

• 6207 - CertusPro-NX: How to inject a soft error using Radiant?

  To inject an error: (1) No need to disable SEDC. (2) Compile the design from Synthesis to PAR. Note: Do not export bitstream yet. (3) Go to Tools>SEI Editor then enable the SEI. (4) Generate SEI bitstream from Radiant's Export Files. (5) Program the ...

• 7357 - All Nexus: What are the input and output signals timing sensitivity of SEDC IP?

  All SEDC input signals will be accepted asynchronously since they will be synced automatically by the SEDC IP internal synchronizer, while SEDC output signals will be synchronous with the input clock (cfg_clk_o of the internal oscillator).