The time to program a Lattice FPGA is dependent on several factors including configuration mode, programming speed, and device size. Some configuration modes and methods are faster than others. The complete configuration time inherently includes both the initialization time plus the time to configure the device. The configuration time is also dependent on the size of the device (memory required to configure the SRAM cells) and speed (frequency) of the configuration logic to process the programming information. The following discussion will detail the steps for users to further understand and calculate programming times.
The initialization time is the time needed from the settling of device power-up until the device can accept programming data. This time is related to the characteristics of internal circuitry within the device. This initialization time varies between slave and master programming modes. This time is specified in all Lattice data sheets (parameter tiCFG).
The maximum programming frequency that can be achieved for the Lattice devices are specified in the device specific data sheet (parameter fCCLK). In master modes, the FPGA internally generates the CCLK configuration clock signal. This is a common practice with SPI flash devices or PROMs. By default, when the FPGA is in master mode, the CCLK frequency starts out low but can be increased using the MCCLK bit stream. The MCCLK_FREQ control is available for the user to select a master clock frequency that best matches the external memory device. The maximum supported master clock frequency setting depends on the read operation specifications for the external memory device storing the bit stream. The MCCLK_FREQ parameters can be adjusted by the user by the Global preference setting in the Lattice design software. A faster memory enables faster configuration. The FPGA-generated clock output frequency varies with process, voltage, and temperature. The fastest guaranteed configuration rate depends on the slowest guaranteed CCLK frequency, as shown in the Lattice device-specific data sheet.
Slave configuration modes enable you to program devices with another device.
In this mode, an external clock source, such as a microprocessor and another FPGA is required. Data is loaded at one bit per CCLK pulse. These modes have no relationship to the in MCCLK_FREQ used with master modes.
At the same clock frequency, parallel configuration modes are inherently faster than the serial modes because they program many bits at a time while slave modes using external clocks allow the FPGA allow faster clocks.
The size of the bit streams are related to the FPGA array size and overhead for optional features such as embedded memory blocks(EMBs) and encryption formats for security. The bit stream sizes are specified in the Lattice device-specific sysConfig Users Guide.
Users can calculate the programming time of the devices using the before-mentioned specifications available in the Lattice documentation. Please see the example calculation below.
Example: A LatticeECP3-95 device in Slave-Parallel PCM mode, and the CCLK is 33 MHz, the maximum EBR preload is 22.5Mb, and an 8-bit parallel bus, then configuration time is 22.5 Mb/(8b*33 MHz) = 0.086 seconds (86 milliseconds). When the initialization time for the LatticeECP3 device in slave mode is 6mS, then the total programming time is 6mS+86mS=92mS.