7757 - Radiant Programmer: What is Erase, Program, Verify Quad 1 operation used for?
Description:
Erase, Program, Verify Quad 1 enables that QE bit to '1'.
In general, there are two (2) requirements/steps to enable booting from external SPI Flash through x4 (QUAD Mode)
Step 1 - Convert the bitstream file into hex (Quad I/O read mode) - this is for the FPGA to switch from 03h mode (standard x1 SPI read mode) to Quad I/O read mode (EBh)
Step 2 - The SPI Flash target for booting must have an enabled QE (Quad Enable) bit, this is for the SPI Flash device to recognize the Quad I/O Read (EBh) command and be able to switch its read mode properly to Quad. Erase, Program, Verify Quad 1 enables that QE bit to '1'
In addition:
- There are SPI flash devices that by default, the QE bit is '0' which means the user needs to perform this EPVQ1 operation to set it to '1'
- There are SPI flash devices that by default, the QE bit is '1' and there is no need to perform EPVQ1 - one example is MachXO5-NX, the internal flash is 32Mbit flash from Winbond which already has a QE bit set to '1'. Thus only Step#1 is required.
- It is case to case basis. The user must check their SPI Flash datasheet to know if steps#1 and #2 will be required.
- The EPVQ1 is the same as Erase, Program, Verify only that additionally, it enables the Quad Enable (QE) bit of the SPI flash. The QUAD there does not mean that the programmer uses 4 data lines during programming, our programmer SW + HW is always in x1 serial so programming time will not be faster. When Quad Mode is enabled in reference to #1 and #2 steps, it only affects the booting (faster).
- Lattice support Quad (x4) SPI booting.
- Lattice do not support Quad (x4) for programming. Radiant programmer, programming cable - these tools only support x1 mode in programming.
Reference:
FPGA-TN-02099-3.4 - sysCONFIG User Guide for Nexus Platform
Technical Note
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