6582 - All Nexus: Referring to SED/SEC User Guide for Nexus Platform (FPGA-TN-02076):In ‘Frame n’, there is significant latency between sedc_errc_o asserting and sedc_err_o asserting. What is causing this latency?
Once an error is detected, the latency basically implies that the hardware goes into error search mode to find the type and location of the error so it can be corrected.
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6291 - CertusPro-NX: Can we use SED/SEC with “sedc_cof_i = 1” for production?
Definition: Yes, the set sedc_cof_i can be set to high or 1 for production. In this manner, the SED/SEC flow will continue to the next frame even error has been detected. In the scenario that sedc_cof_i is low, it will stop SED/SEC when ...
7366 - All Nexus: Why does the SEI tool generate frame error locations that exceed the expected total number of frames shown in Table 7.1 of the “Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform [FPGA-TN-02076-1.9]” document?
The address counter or frame number for each frame does not line up linearly. There is a gap when assigning a frame number for each frame, and therefore the data frame number reported in the SEI editor is expected and can be larger than the ...
6584 - CertusPro-NX: Does sedc_err_o and sedc_errm_o implementation of 'sticky' functionality in the Silicon itself or in some soft logic?
Description:sedc_err_o and sedc_errm_o are implemented with "sticky" functionality. "Sticky" functionality is defined as functionality where in the setting persist even through reset. The implementation of sticky bit is implemented in Silicon.
7110 - SEDC: Why does errcrc_o asserts when a correctable error is detected?
The sedc_errcrc_o normally asserts when there is a soft-error detected. It will transition from high to low in the second run if the single-bit soft-error is correctable. To support this, the user has to monitor the 2 clock cycle low pulse of BUSY ...
6121 - Does the Nexus Platform family have an internal access to the configuration area (ex: USERCODE, Unique ID, CFG0, CFG1, etc)?
Referring to the Table 6.14 in FPGA-TN-02099 for non-JTAG command table, this is the command sets for all non-JTAG configuration ports including LMMI. The command sequence should be no difference as described in FPGA-TN-02099 for NON-JTAG slave ...