6121 - Does the Nexus Platform family have an internal access to the configuration area (ex: USERCODE, Unique ID, CFG0, CFG1, etc)?
Referring to the Table 6.14 in FPGA-TN-02099 for non-JTAG command table, this is the command sets for all non-JTAG configuration ports including LMMI.
The command sequence should be no difference as described in FPGA-TN-02099 for NON-JTAG slave configuration interface.
For Nexus Platform LMMI-CFG access, below are the information from Configuration Target Specification:
The command sequence should be no difference as described in FPGA-TN-02099 for NON-JTAG slave configuration interface.
For Nexus Platform LMMI-CFG access, below are the information from Configuration Target Specification:
- The Configuration IP supports LMMI (Lattice Memory Mapped Interface) Slave access.
- The LMMI Slave port provides CFG’s access from the user logic (Fabric) in user mode.
- When user logic want to access any CFG’s internal registers or any other CFG data, it should follow LSC_* command sequence described in FPGA-TN-02099.
- For example to program CFG’s Control Register0, LMMI master should perform 8 back-to-back write transfers (1-Opcode, 3-Operands, 4-Data Bytes).
- In case of CR0 read, LMMI master should perform 4 write transfers followed by 4 read transfers.
- The diagrams represents the CR0 program and read accesses from LMMI interface as shown on below images.
- For any other register access, LMMI master should follow similar sequence. For example, unique ID or USERCODE read, it should be 1-Opcode, 3-operands, 8-Data bytes.
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