Solution: 

Lattice provides the BSCAN2 Intellectual Property as a pre-compiled NGO file that can be inserted into your own designs. The early BSCAN2 NGO files included an instantiation of the Global Set/Reset (GSR) macro. Explicit instantiation of the GSR macro causes all flip-flops in the FPGA to have the GSR_ENABLED attribute assigned TRUE. The implication of this is that the network assigned to the GSR macro SETS/RESETS every flip-flop. By default the GSR macro is attached to the BSCAN2 TRST input. Any assertion of TRST causes all flip-flops in the device to be SET/RESET.

The MAP tool has the ability to alter the network attached to the GSR macro. Any assertion of the new network attached to the GSR macro causes all flip-flops in the design to SET/RESET. This includes the BSCAN2 registers. The BSCAN2 outputs change state as a result.

Lattice has updated the BSCAN2 NGO to eliminate the explicit GSR macro. To eliminate the undesirable reset behavior update your BSCAN2 NGO file and generate a new bitstream for your FPGA.

The latest BSCAN2 NGO files, with the explicit GSR macro instantiation removed, are available for download from the BSCAN - Multiple Port Linker (BSCAN2) webpage on the latticesemi.com.