MIPI CSI-2 / DSI D-PHY Transmitter
6719 - Why does the MIPI-CSI2 receiver not functional when FPGA is booted form flash, but functional in fast configuration?
Try connecting the power-down input of the DPHY-Rx to the power-down signal that drives the sensor. This should resolve the issue.
5485 - CrossLink: Why are there different clock frequencies when building a MIPI CSI-2 bridge?
Description: It is easy to divide or multiple the clocks by power of 2. It is recommended to use divisible or factor by the multiples of 2 such as (2 and 4).
5460 - In D-PHY to CMOS V1.3 for crosslink application, why does v_sync signal not normal compared to the datasheet? When the data valid, V_sync have the low level and when v_sync is high, it have no h_sync.
Waveform found in Fig 2.5 of the documentation has to be updated. For reference on the correct waveform, please refer to byte-to-pixel converter IP, under FPGA-IPUG-02027 to be specific, it is under Fig 2.2.
3505 - iCE40:Does MIPI CSI2 and DSI reference designs supported on iCE40?
MIPI CSI2 and DSI interfaces are not supported on iCE40.
5389 - CrossLink: Why does the generated VHDL code does not contain any ports for CSI2/DSI D-Phy Receiver IP?
Description: CSI2/DSI D-Phy is a submodule IP. This only provides an instantiation templates for vhdl because it is expected that it will be used in a larger design. In addition, generating this IP is done in Verilog.
6069 - [CrossLink-NX] MIPI: What is the time required for the MIPI D-PHY to resume after the power-down mode is de-activated?
The maximum PLL lock time is 5,000 input cycles.
6067 - [CrossLink-NX] MIPI: Why does MIPI CSI-2/DSI DPHY Transmitter IP working on Radiant 2.0 but not on latest version?
If Crosslink-NX device is an ES part, it is only supported by Lattice Radiant 2.0 SP1 Software.
5988 - Lattice Diamond : Error on Synthesis RD1182 : The flow errors out because "aligner_4_on_on" is unexpanded. What is the workaround.
Solution: 1. Directory „rd1182_mipi_dphy_interface_ip\rd1182\source\verilog\ecp5\ngo“ Copy "aligner_4s_on_on.ngo“ to "aligner_4_on_on.ngo“ 2. Strategy -> LSE -> change Macro Search Path to ...
7265 - MIPI CSI-2 / DSI D-PHY Transmitter: What is 'Counter Width' parameter in rx_dphy IP and how to calculate the value?
Details: 'Counter Width' refers to bus width of the counter that tracks the number of rows written during the high-speed data transition. Setting the value for Counter Width is valid only when RX_FIO type is set to 'QUEUE' where high-speed data is ...
5855 - [DPHY-TX of CrossLink] What happen if the length of a long packet is not multiple of 8 bytes?
The user will get unexpected results on both the CRC and WC values.
5813 - [CrossLink] For 2:1 MIPI CSI-2 Bridge Soft IP debugging, what caused hs_sync_ch0 unexpected behavior?
The signals for sp_en is asserted every time there are frame start code, frame end code line start code and line end code through the data type. Line start and line end are optional as per CSI-2 specification v1.1. Thus, to enable in the testbench, ...
6518 - Crosslink-NX: What is the Max Line Rate of Crosslink-NX Soft Dphy for each package for -7 Speed Grade?
Description: LIFCL17 72 WLCSP: N/A LIFCL17 72 QFN: 861 Mbps LIFCL17 121 CSFBGA: 1034 Mbps LIFCL17 256 CABGA: 1034 Mbps LIFCL40 72 QFN: 861 Mbps LIFCL40 121 CSFBGA: 1034 Mbps LIFCL40 256 CABGA: 1034 Mbps LIFCL40 289 CSBGA: 1034 Mbps LIFCL40 400 CABGA: ...
6504 - Crosslink-NX: How can I achieve 2.5Gbps per line for D-Phy TX?
Description: Crosslink-NX can supports 2.5Gbps per line, but when I started D-Phy TX version 1.70, the TX Line Rate per line is 160~1500 Mbps. Solution: In order for the 2.5 Gbps per lane to be supported, you need to change from Gear 8 to Gear 16. ...
5691 - Crosslink / CSI-2/DSI D-PHY Transmitter IP Core : For Crosslink, how can I get the register value from the display(destination)?
DSI-TX IP is only capable of transmission only and do not support bus turn around. This means, it does not support read type of "DCS" command in HS-mode / LP-mode.
6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?
For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...
5606 - CrossLink: When confirming by simulation for CMOS-to-DPHY IP, 16-bit Short Packet Data Filed is output as follows 0,1,0,1,0,1,0,1...... Is this correct?
Description: With regards to frame synchronization, you may refer to section 9.8.1 Frame Synchronization Packets of mipi CSI-2 specification. It states that each image frame shall begin with a Frame Start (FS) Packet containing the Frame Start Code ...