5855 - [DPHY-TX of CrossLink] What happen if the length of a long packet is not multiple of 8 bytes?
The user will get unexpected results on both the CRC and WC values.
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2245 - Lattice ECP3: Is it OK to loop XAUI data from the RX XGMII to TX XGMII if the IPG is always between 5 and 8 bytes long?
Description:The IEEE 802.3ae Specification explains that it is possible for a 12 bytes IPG (Inter Packet Gap) to shrink to 5 bytes by the time it reaches the RX XGMII interface. This is due to many factors, including clock rate compensation. ...
6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.
Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...
5606 - CrossLink: When confirming by simulation for CMOS-to-DPHY IP, 16-bit Short Packet Data Filed is output as follows 0,1,0,1,0,1,0,1...... Is this correct?
Description: With regards to frame synchronization, you may refer to section 9.8.1 Frame Synchronization Packets of mipi CSI-2 specification. It states that each image frame shall begin with a Frame Start (FS) Packet containing the Frame Start Code ...
7681 - Pixel-to-Byte IP v1.7.0: Why do I encounter interruption on the MIPI long packet transmission after a while when connecting lp_en_o from P2B v1.7.0 to lp_en_i of DPHY_TX? However, when I delay the lp_en_o by one clock and then connect to DPHY TX,
The lp_en flag needs to be delayed depending on the data type / number of pixel lanes. User would need to fine tune between the lp_en_o and lp_en_i to get the correct transmission.
6149 - Crosslink: In dphy_rx_wrap_beh.v, how do user resolve error related to port size mismatch?
- In dut_inst.v and dut_inst.vhd, the lp_hs_state_d_ port should be lp_hs_state_d_0. - In rx_dphy.v, the following should be inputs: input lp_d0_tx_en_i, input lp_d0_tx_p_i, input lp_d0_tx_n_i.