5813 - [CrossLink] For 2:1 MIPI CSI-2 Bridge Soft IP debugging, what caused hs_sync_ch0 unexpected behavior?

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• 6140 - Crosslink: Is there any CSI-2 test pattern generator?

  In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...

• 6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?

  For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...

• 6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?

  Description: Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document. 'syn_clk_i' does not need to synchronize with any clocks, and ...

• 5923 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Can the DSI to CMOS IP be changed to DPHY1 from DPHY0?

  The user can change the hardened D-PHY blocks location between DPHY0 and DPHY1 by adding a LOCATE preference in the .lpf file to SITE "MIPIDPHY0" or SITE "MIPIDPHY1". The LOCATE preference is the following, for example: LOCATE COMP " ...

• 6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.

  Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...