6719 - Why does the MIPI-CSI2 receiver not functional when FPGA is booted form flash, but functional in fast configuration?

• Related Articles

• 6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?

  For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...

• 6140 - Crosslink: Is there any CSI-2 test pattern generator?

  In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...

• 6519 - MIPI CSI-2 / DSI D-PHY Receiver: What is the use of the RX_FIFO in the MIPI D-phy RX IP?

  Description: RX_FIFO is used when clk_byte_fr_i and clk_byte_o does not have the same frequency and/or is not synchronous, therefore it is used in order for the clocks to be synchronized and run at the same frequency. Nowfor the FIFO we introduce the ...

• 3624 - LatticeECP3: What are the supported rates for Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI) on Lattice ECP3?

  The supported rates for the MIPI CSI RX and TX on Lattice ECP3 -8 speed grade are 550 Mbps and 756 Mbps respectively.

• 5879 - CrossLink: How to configure the Reference Design MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for DSI single lane?<div><br></div>

  Please refer to FPGA-RD-02060 Section 3, Design and Module Description. On the project file, modify the rx_dphy which is declared under rx/rx.sbx. On the Receiver section of the IP, modify the RX Interface to DSI and the Number of RX Lanes to one.