5389 - CrossLink: Why does the generated VHDL code does not contain any ports for CSI2/DSI D-Phy Receiver IP?
Description:
CSI2/DSI D-Phy is a submodule IP. This only provides an instantiation templates for vhdl because it is expected that it will be used in a larger design. In addition, generating this IP is done in Verilog.
Related Articles
5923 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Can the DSI to CMOS IP be changed to DPHY1 from DPHY0?
The user can change the hardened D-PHY blocks location between DPHY0 and DPHY1 by adding a LOCATE preference in the .lpf file to SITE "MIPIDPHY0" or SITE "MIPIDPHY1". The LOCATE preference is the following, for example: LOCATE COMP " ...
5691 - Crosslink / CSI-2/DSI D-PHY Transmitter IP Core : For Crosslink, how can I get the register value from the display(destination)?
DSI-TX IP is only capable of transmission only and do not support bus turn around. This means, it does not support read type of "DCS" command in HS-mode / LP-mode.
6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?
Description: Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document. 'syn_clk_i' does not need to synchronize with any clocks, and ...
6519 - MIPI CSI-2 / DSI D-PHY Receiver: What is the use of the RX_FIFO in the MIPI D-phy RX IP?
Description: RX_FIFO is used when clk_byte_fr_i and clk_byte_o does not have the same frequency and/or is not synchronous, therefore it is used in order for the clocks to be synchronized and run at the same frequency. Nowfor the FIFO we introduce the ...
5919 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Why do I get this error message like this: "ERROR - IO register/latch csi2_to_cmos_inst/inst1_inst/lv_ff cannot be implemented in PIC."?
Description: This is caused by forcing a register whose input is being traced to be implemented as an input flip-flop because of a preference, USE DIN. Solution: The user should allow the register to be implemented as an internal flip-flop by ...