Reveal Inserter / Controller
7650 - Radiant 2023.2 SP1 to Radiant 2024.1 SP1 Reveal Analyzer: signal appears to hang or reset
Description: When opening Reveal Analyzer, signals will appear to reset or hang. The Reveal version in Radiant being used includes the following: 2023.2 SP1, 2024.1, 2024.1 SP1. Solution: This is a known issue and is planned to be fully fixed in ...
7469 - Lattice Reveal: What should be checked if a Reveal Error <i>Core0 incorrect pattern readout</i> is encountered?
First, try to adjust the TCK Low pulse width delay to a certain value (usually between 5 and 10). This can be done in the �Design > Cable Connection Manager� settings. If above suggestion does not solve the error, verify the following items: (1) ...
5314 - Is Reveal supported with Platform Manager 2?
Reveal is not supported in the native Platform Designer interface of Diamond. However, the Verilog can be exported from Platform Designer. The exported design can be opened as a normal Diamond project, and then Reveal can be added to that design. The ...
5075 - How to use Reveal with Soft JTAG for debugging the design?
See the following example from the CrossLink/LIFMD device family, which does not provide a hard JTAG block. Therefore, Reveal JTAG support is implemented using Soft JTAG debugger logic and GPIO pins will be used for four JTAG pins (JTAG_TCK, ...
2795 - Diamond: How do I create a new Reveal Analyzer file without deleting an existing .rva file in my Lattice Diamond project directory?
Reveal Analyzer Wizard launched by clicking on Reveal Analyzer button creates a new .rva file only if there is no .rva file in your Lattice Diamond project directory. You cannot create a new Reveal Analyzer file with Reveal Analyzer Wizard with ...
380 - ispLEVER Classic/Diamond Reveal Analyzer: using a JTAG chain with multiple devices
Reveal Logic Analyzer can be used for On-Chip Debug even if the targeted device is a JTAG chain with multiple devices. Use ispVM to define the JTAG chain and the position of the targeted device in the chain. Then, save the chain (.xcf) file and ...
2692 - Reveal: How do I get further detail for the "Failed to read design" error message in Reveal Inserter?
When the design input is RTL, Reveal Inserter has to read or parse the design to provide the list of debug-able internal nodes. If it encounters errors, Reveal Inserter simply reports "Failed to read design". As Reveal Inserter uses the same parser ...
1292 - Mico32: How to use Reveal to debug?
A typical issue in debugging a new system design is that an error becomes apparent to a software algorithm, but the software and GDB debugger have no visibility into the internal logic of a component that may be producing errors. For example, a new ...
6903 - Radiant 2023.1 and earlier: Does Reveal Inserter support Avant G and X?
Description: Complete support of Avant products starts at the release of R2023.2. Solution: No, the support for Avant G and X to use Reveal Inserter will start on Radiant 2023.2.
7276 - Radiant: IP signals are grayed out in Reveal Inserter
Description: In Radiant, users may see that they are unable to trace some IP signals in Reveal Inserter. It will appear grayed out like the following: Solution: Please check if the IP you are using has an option to remove Tristate Buffers. If so, ...
6330 - Diamond 3.12 and below: Error "'attributes' is not compiled in library 'synopsys'"
Description: When adding Reval to your design, and try to synthesize, below error might occur: Error "'attributes' is not compiled in library 'synopsys'" Solution: This is a known issue in Diamond version 3.12. Please try to update the software to ...
6879 - Radiant: How to resolve "Done Error Code 1" when Reveal core is added to a VHDL design?
This issue will occur on designs that have VHDL library cyclic dependencies. To remove the error, modify your design to eliminate all library cyclic dependencies before adding Reveal.
6857 - Lattice Radiant: How to properly handle the Reveal Controller's Virtual Switch in Radiant when use in input such as user-reset?
The virtual switch should be tied to a net in this case, the recommended implementation is shown below in Verilog syntax: assign rst_n = (~virtual_sw);
6276 - Diamond 3.12 and below: Error: "'attributes' is not compiled in library 'synopsys'"
Description: When adding Reveal into a VHDL-based design in Diamond 3.12 and below versions, below error might occur during compilation: Error: "'attributes' is not compiled in library 'synopsys'" Solution: This issue only occurs when using Diamond ...
6271 - Reveal Analyzer core0 error: How to check the JTAG cable connections?
When the user connects the 2B programming cable with color-coded flywires to the board, Reveal only uses 4 wires + VCC and GND: * white = TCK * purple = TMS * orange = TDI * brown = TDO * red = VCC * black = GND If the user has connected a yellow ...
7162 - Diamond version 3.13 Reveal Analyzer fails when using a HW-USBN-2A cable on a machine with an Intel CPU: ERROR - failed to set cable port (cable:USB port:EzUSB-0 error:-1).
Description: In Diamond version 3.13, when using a HW-USBN-2A cable on a machine with an Intel CPU, Reveal Analyzer may fail with the following error: ERROR - failed to set cable port (cable:USB port:EzUSB-0 error:-1). Solution: There is no planned ...
7318 - Radiant version 2023.2 SP1 and older: How do I change the TCK Low Width Delay to above 10x in Reveal Analyzer?
Description: See the following steps to set the TCK Low Width Delay to >10x: 1. Program a device with the Reveal core 2. Create a .rva file 3. Edit the .rva file in a text editor. Change the following line:
6575 - Lattice Nexus devices using Reveal: no output from LVDS IP
Description: While debugging your Radiant design using Reveal, users may observe that there is no output from their LVDS IP. Solution: When Reveal is inserted in Nexus devices, on certain designs, the GSR net gets assigned to a reset signal that may ...
6545 - Diamond: Why does Reveal Inserter with CrossLink device only allows one trigger expression?
Since Crosslink does not have a hard JTAG circuit, it uses soft JTAG for Reveal Debugger and can only support one Trigger Expression (TE) and does not support Final Trigger Counter. You can refer to below FAQ link for the steps on using the soft JTAG ...
6538 - Reveal Inerter synthesis error:<span style="color: rgb(224, 62, 45);"> <reveal signal name> with mode 'out' cannot be read.
Description: The issue is reproducible using a simple mixed-language design (VHDL + Verilog) wherein Verilog is set as the top module. Solution: This is a bug on the software verific for Radiant 3.2 or below. This happens when VHDL instantiates the ...
5977 - Diamond: What environment variable allows users to see the internal Reveal file when Reveal Inserter / Analyzer is implemented?
"KEEP_REVEAL_TEMP" is the environment variable. It needs to be set to 1. When set to 1, users can see the internal Reveal file in a folder under the implementation folder. This is called "reveal_workspace" or "reveal_temp".
5937 - Reveal Analyzer on iCE40 Ultraplus Breakout Board: What is the common cause of core0 incorrect pattern readout?
One common cause for this issue for iCE40 Ultraplus Breakout boards is failing to use the HW-USBN-2B cable as shown on page 43 of the tutorial. Here's a direct link to the document: http://www.latticesemi.com/view_document?document_id=52758 Unlike ...
6453 - Nexus devices with Reveal: boot issue
Description: If not implemented properly in the design, GSR might unintentionally cause boot issues. Solution: Please try setting the Force GSR to "False" in the SynplifyPro/LSE and Map Design strategy settings. If the problem persists, please file a ...