Therefore, Reveal JTAG support is implemented using Soft JTAG debugger logic and GPIO pins will be used for four JTAG pins (JTAG_TCK, JTAG_TDI, JTAG_TMS, and JTAG_TDO).

The following steps should be followed while using Soft JTAG Debugger:

• Create / Open a Lattice Diamond Project.
• Create/Configure Reveal to the design via Reveal Inserter.
• Steps to add Reveal are the same for CrossLink also as in the Reveal User Guide but need to specify the JTAG Pins manually. 
• To create a new Reveal Inserter, click on the icon of Reveal Inserter or Go to the Tools menu and choose Reveal Inserter. 
• Configure the Reveal Inserter
• Add signals to be traced in the Trace box in Reveal Inserter. 
• Specify the sample clock 
• Set the Trigger Unit 
• Set the Trigger Expression
• Save the Reveal Inserter.
• Add/Insert the Reveal Inserter into the Diamond Project.
• The tool will automatically add a Soft-JTAG logic when the Reveal is inserted into the design.
• Need to specify these pins manually 
• Click on the OK button to continue
• Make sure the Reveal Inserter is active
• The name of the Reveal Inserter file will be highlighted in bold if the Inserter is active, else right-click on the Reveal Inserter file and choose ‘Set as Active Debug File’ to insert the Reveal into the design
• Run through Synthesis and Map.
• Open the Spreadsheet View from the Tools menu. Users will notice the new IO with JTAG naming has been automatically added to the design. Assign these pins to the GPIO corresponding to the appropriate header pins on the board. The same can be done through the LPF file also.
• Locate pins JTAG_TCK, JTAG_TDI, JTAG_TMS, and JTAG_TDO on the same bank, preferably bank-0, and leave bank-1/bank-2 available for DDR, MIPI or LVDS usage.
• Locate the JTAG_TCK pin to PCLK or GR_PCLK to avoid using general routing, as clock general routing may violate the CLK 1-PLC rule. For an example of the LOCATE preference:
  LOCATE COMP "JTAG_TCK" SITE "F2"
• Set a FREQUENCY preference as follows:
  FREQUENCY PORT "JTAG_TCK" 6.000000 MHz;
• Make sure that the pins used for Reveal are not connected to other circuitry to avoid contention.
• JTAG pins will be removed if Reveal is made inactive
• Continue the design flow and generate a bitstream. 
• Programming the FPGA
• Reveal Analyzer requires the design with Reveal Inserter running on the device.
• Open the Programmer and program the device.
• If the user gets MachXO3LF after scanning, use the other port.
• The status of the Programmer can be seen on the Output window as shown below
• Connect the USB cable. (Both 2A and 2B cables will work.)
• Connect the TCK, TDI, TDO, and TMS wires of the USBN-2A/2B cable as per the pin assignments on the board. 
• Also, Connect the GND and VCC of the cable to the ground pin and bank VCCIO pin of the device

Note: If there was a previous run on Diamond Programmer to configure CrossLink, then the user may need to open Windows Task Manager and end the cableserver.exe process to allow Reveal Analyzer to access the USB cable.

• Starting Reveal Analyzer
• To create a new Reveal Analyzer, click on the icon of Reveal Analyzer or 
• Go to Tools menu > and choose Reveal Analyzer 
• Then provide the file name, detect the USB port, Scan the Debug device, and Browse the RVL source (*.rvl file)
• Running Reveal Analyzer
• The Reveal Analyzer should look like as shown below.
• Click on the play button to run the analyzer.
• Reveal Analyzer first configures the cores selected for the correct trigger condition, then waits for the trigger conditions to occur.
• When the Reveal Analyzer is running and no trigger condition is met, the Reveal Analyzer will be in Running State and will be as shown below
• The Run button changes to the Stop button
• If the trigger condition is met, the Analyzer will show the captured data as shown below.

For more information, please refer to the Reveal User Guide from the Start Page of the Lattice Diamond tool.