7469 - Lattice Reveal: What should be checked if a Reveal Error <i>Core0 incorrect pattern readout</i> is encountered?
First, try to adjust the TCK Low pulse width delay to a certain value (usually between 5 and 10).
This can be done in the �Design > Cable Connection Manager� settings.
If above suggestion does not solve the error, verify the following items:
(1) Stable and continuous clock is used.
(2) Important nets are not optimized or there is no disconnected component/module.
(3) JTAG connection is good.
(4) There is no unused output ports with the same bank on the Reveal clock pin. To solve this, make sure to constraint it using ldc_set_locate.