Radiant: How to resolve "Done Error Code 1" when Reveal core is added to a VHDL design?

This issue will occur on designs that have VHDL library cyclic dependencies. To remove the error, modify your design to eliminate all library cyclic dependencies before adding Reveal.

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Lattice Radiant and Diamond: How do i resolve core0 error when Running reveal analyzer? How to resolve Error "Core0 incorrect pattern readout" while running Reveal Analyzer?
Description: When running the reveal analyzer a "Core0 incorrect pattern readout" error is encountered causing the tool to not generate its desired waveforms. Solution: This can be resolved by making sure that you have the following: 1) JTAG TCK is ...
Lattice Diamond: Why does my design with Lattice Sentry i2c filter core failed compilation with "Synthesis exit by 9" and "Done: error code 9" error message?
Description: Users utilize i2c filter encounter Synthesis Exit by 9 when synthesizing their design on Diamond Solution: This is due to wrong FPGA tool selection on the IP parameter. Make sure you choose the correct software tool in the IP core ...
ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?
In Diamond version 3.14, there is a bug where it incorrectly limits the number of PLLs in the device to 0 for LFE5U-12F. Example error message: ERROR - (device oversize error). The number of PLL components needed (1) exceeds the number available. ...
Diamond 3.12: Why is it that error was detected when using VHDL 2008 with Reveal? <div><br></div>
Description: After synthesis, specific error produced by the tool is stated as below: C:/lscc/diamond/3.12/cae_library/vhdl_packages/../../ispfpga/vhdl_packages/vh2008/ieee/syn_misc_2008.vhd(22): ERROR: 'attributes' is not compiled in library ...
5075 - How to use Reveal with Soft JTAG for debugging the design?
See the following example from the CrossLink/LIFMD device family, which does not provide a hard JTAG block. Therefore, Reveal JTAG support is implemented using Soft JTAG debugger logic and GPIO pins will be used for four JTAG pins (JTAG_TCK, ...

Radiant: How to resolve "Done Error Code 1" when Reveal core is added to a VHDL design?

Radiant: How to resolve "Done Error Code 1" when Reveal core is added to a VHDL design?

Related Articles

Lattice Radiant and Diamond: How do i resolve core0 error when Running reveal analyzer? How to resolve Error "Core0 incorrect pattern readout" while running Reveal Analyzer?

Lattice Diamond: Why does my design with Lattice Sentry i2c filter core failed compilation with "Synthesis exit by 9" and "Done: error code 9" error message?

ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?

Diamond 3.12: Why is it that error was detected when using VHDL 2008 with Reveal?&nbsp;<div><br></div>

5075 - How to use Reveal with Soft JTAG for debugging the design?

Diamond 3.12: Why is it that error was detected when using VHDL 2008 with Reveal? <div><br></div>