2295 - Reveal: How can I resolve the Reveal error: core0 incorrect signature (RVL: 154782948 != Device: 0)
A signature mismatch with a reported signature of 0 almost always means the sample clock is not correct. The typical reasons are it’s too slow, or not a free running clock. Usually, the frequency of the sample clock should meet its timing constraint if the timing constraint is specified, and the frequency of the sample clock is at least 3 or 4 times that of the JTAG clock.
You should also ensure that the sample clock is running all the time. If you need to capture data at a specific time, you can use a clock as sample enable. The data capture only happens when the sample enable is active, that is, the clock as sample enable may turn sampling on and off.
You can refer to the sections Setting Required Sample Parameters and Setting Sample Options in the Reveal User Guide for more information on the frequency of the sample clock and sample enable.
In addition to the above, you can also try to resolve this error in other ways:
1. Clear up the project including the Reveal related files, then insert Reveal again, and compile the project, to see if the error disappears, in case some files are out of date or are not generated.
2. Use the other USB port or parallel port on your computer in case there is some problem with your port.
3. Ensure that you are using the programming cable made by Lattice as other cables probably do not support Lattice Reveal Analyzer.