6857 - Lattice Radiant: How to properly handle the Reveal Controller's Virtual Switch in Radiant when use in input such as user-reset?
The virtual switch should be tied to a net in this case, the recommended implementation is shown below in Verilog syntax:
assign rst_n = (~virtual_sw);
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7650 - Radiant 2023.2 SP1 to Radiant 2024.1 SP1 Reveal Analyzer: signal appears to hang or reset
Description: When opening Reveal Analyzer, signals will appear to reset or hang. The Reveal version in Radiant being used includes the following: 2023.2 SP1, 2024.1, 2024.1 SP1. Solution: This is a known issue and is planned to be fully fixed in ...
6771 - Radiant 2023.2 SP1 or earlier: How can user handle clock-domain-crossing (CDC) paths timing violations between rvlclk and another clock of the design (clk)?
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6737 - Radiant: Does Radiant perform static timing analysis (STA) on reset pins/signals?
Radiant performs static timing analysis (STA) on reset pin/signals that are using Local Set/Reset (LSR). To use LSR, user need to make sure that the GSR-related strategy settings are False/OFF (Force GSR on Synthesis and Infer GSR on MAP). User also ...