Reveal Inerter synthesis error:<span style="color: rgb(224, 62, 45);"> <reveal signal name> with mode 'out' cannot be read.</span>
Description:
The issue is reproducible using a simple mixed-language design (VHDL + Verilog) wherein Verilog is set as the top module.
Solution:
This is a bug on the software verific for Radiant 3.2 or below.
This happens when VHDL instantiates the Verilog module with a trace/trigger signal that uses an uppercase signal name.
Example:
under file1.v:
module verilog_top #(
parameter REG_WIDTH = 8)
(input wire CLK1,
input wire [REG_WIDTH - 1:0] D1,
output wire [REG_WIDTH - 1:0] Q1);
under file2.vhd:
verilog_inst : verilog_top
generic map (
REG_WIDTH => REG_WIDTH0)
port map(
CLK1 => clk0,
D1 => d0,
Q1 => q0
);
The workaround is to use lowercase naming under Verilog or SystemVerilog module.
Using the example above, instead of the signal name "D1", use "d1".