Board Design Consultation & Schematic Review
7748 - Why is there a mismatch between the hardware checklist and the evaluation board circuit design?
Description: The customer has observed discrepancies between the design recommendations provided in the Hardware Checklist and the actual design implementation on the Lattice Evaluation Board. Reason: Hardware Checklists are developed after ...
1071 - How to resolve simultaneous switching output (SSO) ground bounce problems/simultaneous switching output sso ground bounce vcc droop noise
As a workaround, user may try the following guideline to reduce SSO noise: 1. Add decoupling capacitors for all VCC/GND Pairs. 2. Place the decoupling capacitors as close as possible to the power and ground pins of the device. Put small capacitors ...
3272 - ECP3: How close can the DDR2 (double data rate) memory be placed to the LatticeECP3-35 device while designing a PCB?
The DDR2 (double data rate) memory PCB trace length should be equal to or less than 3.0'' for the LatticeECP3-35 device. It is recommended to have an even shorter than 3.0'' trace length for the DDR2 memory to achieve better results.
1749 - Power Manager II: How do I design a PCB land pattern for Power Manager to meet UL standards?
Designing circuit boards to meet safety certification agency requirements is a very complex subject, and the requirements you need to meet also vary by product and geographical market. For example, two common requirements for PCB design are for for ...
852 - Should I add external series resistors to my parallel bus to improve the signal integrity?
Description: A device is driving a large number of IOs that switch between VCCIO and GND in a parallel data bus. The designer knows that with an unterminated bus there can be reflections if the signal traces are too long which could decrease the ...
851 - Can I drive long PCB traces with an LVCMOS output?
Yes. When using the LVCMOS output settings with long 50 ohm PCB traces or cables, you will need to use the IO's higher output current settings and add an external 33 ohm series resistor for a good 50 ohm source termination with minimal ringing at the ...
850 - Why can't I drive a long PCB trace with a low current setting and get good signal quality?
LVCMOS IOs driving long PCB traces will often show overshoot at a receiver when the IO output current setting is high. When the IO output current setting is low, the waveforms received can be somewhat distorted on a long PCB trace. This is a common ...
848 - Should I add a series inductor between my voltage regulator output and VCC core?
No. There are relatively high currents flowing in the VCC core, both static and dynamic. The added series L would introduce both additional series resistance and a time delay in the regulator's response to the large dynamic current changes required ...
6040 - CrossLink: What is the layout recommendation for LIA-MD6000-6KMG80E?
If we are referring to tables 3.1 and 3.2 in FPGA-TN-02024 (PCB Layout Recommendation document), we will use the same value for ctfBGA. In this case, 0.300 for SMD and 0.200 for NSMD. This is also reflected in Table 3.2
832 - Power Manager II: How to implement multiple POWR1220AT8 Power Manager devices on a board?
There are several ways to do this. In some cases the functions inside a Power Manager II device may be stand alone and not affect the other device controlling other supplies. In the case where there are zones or sections that need to get powered up ...
813 - ispClock: How to implement low-cost CMOS oscillator with ispClock 5400D devices?
While the reference clock input of the ispClock5406D and ispClock5410D are differential, they can be driven from a single-ended CMOS oscillator. This offers lower overall board costs compared to higher cost options. You may refer to "AN6080 - Using a ...
791 - What type of pull ups are required for JTAG signals?
User may refer to respective device Hardware Checklist for sysCONFIG port pins pull up requirements. Example: MachXO3D hardware checklist
738 - How should user connect unused I/O pins in a Lattice device?
I/O pins which are unused in a design typically do not need to be grounded or connected anywhere. Some of the devices have global setting for pull-ups on I/O likes -Up, -Down or Bus-Hold, and others may have settings for each pin. By default, Lattice ...
5987 - Platform Manager 2: What is the ISPPAC-POWR1220AT8-01T100I junction to case resistance?
The Lattice Thermal Management document provides these details and can be found here: http://www.latticesemi.com/view_document?document_id=210 Page. 9, Table 3.1 gives the package data for the TQFP 100, 1.4mm for Package Thermal Resistance
730 - MachXO: Why do external pull up required for MachXO SLEEPN pin?
The SLEEPN pin on the MachXO device is a control signal for the internal regulator. If the pin is pulled low it puts the device into a low power state. Although the SLEEPN pin has a weak internal pull-up, an external pull-up is recommended if the pin ...
2855 - Power Manager II: Do I need to connect a 100 ohm series resistor between monitored voltages and VMON pins on the POWR1220AT8 device?
No, you can connect the VMON pins directly to monitored voltages which are between 0 and 5.9V. Some of the Lattice evaluation board schematics do include a resistor between the monitored voltage and the VMON pins. This is typically only used with the ...
2130 - Power Manager II: We found a sensitivity on the resetb pin of POWR1220AT8 - measuring voltages on that pin with a multimeter have triggered resets of the device. Is there any recommendation for reducing noise sensitivity on that pin?
A 0.01 uF capacitor can be added to the RESETb pin to reduce the sensitivity to noise in certain applications.
6310 - LatticeECP2/M
BSDL files can be generated using the Diamond Deployment tool: Step 1: Open Deployment Tool Step 2: Select "Create New Deployment" > Select "File Conversion" > =Select "Application Specific BSDL File" Step 3: Upload JEDEC file and Select Desired ...
4706 - iCE40: Do we have any recommended LDO for iCE40 devices ?
We do not have any specific recommended LDO. The VCC for iCE40 devices has a 5% tolerance. It should be easy to find a regulator having a tolerance within 5% for -40°C to +85°C temperature range.
5978 - Platform Manager 2: When using the HVMON for 12V voltage monitoring of HIMONN_HVMON pin, where to connect the HIMONP pin?
When only using HIMONN_HVMON to measure voltage, connect HIMONP to the same source to prevent differential over-voltage.
6305 - MachXO: Where to find the automotive BSDL files?
The automotive BSDL files for MachXO should be the same functionality as the standard device files on the website.
674 - POWR1014/A: Why should user avoid supply power to POWR1014's VCCPROG pin when VCCA and VCCD pins are powered on?
Description: Power must NEVER be supplied to the VCCPROG pin when VCCD and VCCA are powered on. Operation under these conditions is undefined and may result in erroneous operation. User should supplied power to the VCCPROG pin on POWR1014 only when ...
5953 - Platform manager 2/ECP5/ECP5-5G
Dual Boot Mode uses the MCLK as a clock source for the external SPI PROM in user-mode. This requires a pull-up to meet the required rise time of the external SPI flash device. When operated in Dual Boot Mode, the MCLK is an output that needs a ...
1674 - LatticeECP2/M: Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?
Unlike LatticeECP3 and LatticeSC families which have programmable termination for LVDS IO, LatticeECP2/M family does not have an on chip termination resistor for FPGA IO in LVDS input mode.
1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?
For generic FPGA input reference clock, DC coupling is what needs to be selected. The generic FPGA IO buffer architecture structure does not support AC coupling. Note: Dedicated SERDES reference clocks that have a CML buffer, can be AC or DC coupled. ...
508 - Why can't I drive a long PCB trace with a low current setting and get good signal quality?
LVCMOS IOs driving long PCB traces will often show overshoot at a receiver when the IO output current setting is high. When the IO output current setting is low, the waveforms received can be somewhat distorted on a long PCB trace. This is a common ...
2674 - PAC Designer: In Trim Configuration Options, what does "Open External Resistors(s) Threshold" imply?
PAC designer software Trim Configuration utility calculates values of resistors connected between Power Manager and DC-DC converter for trimming the DC-DC conveter output. In Trim Configuration options the "open external resistor threshold" ...
7238 - Certus-NX: What to do with an unused SerDes power supply and other pins?
Description: When SerDes is not used, there are proper states for unused pin. Solution: Connect VSSSD, Rx Differential Inputs, SD_EXTx_RefCLKx, SDQx_RefCLKx, and RefRETx to board ground. Then, leave VCCSD0, VCCPLLSD0, VCCAUX, SDx_REXT and Tx ...
2655 - Platform Manager 2: Is there a low cost way to power the ProcessorPM-POWR605 off of a 5V rail?
Depending on the nature of the 5V rail, the ProcessorPM-POWR605 can be powered using a simple voltage divider. This very low cost solution uses a stable 5V supply with an attenuator circuit. The 3.3V rail is developed from a voltage divider using 120 ...
2646 - I changed my design and now it works for a brief amount of time and then begins to fail, what can cause this?
Description: A new board design has been operating correctly during initial testing, the FPGA design was changed to add the full feature set and now the new design begins to fail after a short amount of time. What could cause this? Solution: Have you ...
2072 - What is the optimum PCB solder mask opening and pad diameter for a Lattice package?
Solution: This question is best answered by reviewing table 3.2 in FPGA-TN-02024. In the table, the Solder Mask Defined (SMD) and Non Solder Mask Defined (NSMD) PCB processing values are given. For the question of which type to use (SMD vs. NSMD), ...
1592 - How much duty cycle variation will a clock signal have at an output IO?
The answer to the amount of duty cycle variation a clock signal can have at an output IO depends on several factors: Clock source characteristics (frequency, rise time, fall time, duty cycle, DC offset) Use of the clock source within the device (PLL, ...
5816 - iCE40 LP/HX: Is there a list of a recommended diode for VPP_2V5 voltage like the one on many iCE40 eval boards?
The main purpose of this diode is to drive the 3.3 V supply down to a voltage within the datasheet requirements for the VPP_2V5 pin during NVCM programming. From page 19 of our document FPGA-DS-02029-3.5, this is stated to be a minimum of 2.30 V to a ...
6532 - What is the recommended Bypass Capacitor size for DDR3 Power filter? Can I use a small capacitor due to my board's limited space?
The recommended Bypass capacitor size is 0603. Yes, 0.1uF capacitors can be smaller than 0603, it is also recommended to use of 0402 or 0201 size capacitors. Using smaller capacitors can improve performance when its mounting bias are in pads or off ...
6531 - Certus-NX: What are the recommendation on power filtering for DDR3? (BYPASS CAPACITORS TO GROUND, VDD, OR BOTH)
All three methods of connecting DDR bypass capacitors can work well, to ground / to VDD / or to both. The key is to minimize the inductance of bypass capacitor connections to improve performance, bypassing to the closest PCB reference plane (VDD or ...
6530 - Why are the power rails for DDR3_VTT and VCC_1V5 connected to one another?
The DDR3 VCC_1V5 powers the DDR3 and the DDR3_VTT is the data buss termination, by using de-caps from DDR_VTT to gnd and VCC_1V5 the data buss is stabilized and centered between the power rails for better signal integrity for all data patterns.
6176 - MachXO2/MachXO3: Why there is no JTAG external pullups (TDI,TDO,TMS) recommendation in our documents such Hardware Checklist and Programming and Configuration user guide while external pull-ups were added in our Lattice demo and evaluation boards.
MachXO2 and MachXO3L/LF TDI,TDO,TMS signals have internal pull-ups, so external pull-ups are not required. However, good engineering practice for a critical bus like JTAG is to augment the internal pull-ups with external if the bus will not always be ...
2567 - ECP3: What are the recommendations for a flex cable that connects a sensor to the Lattice HDR-60?
Solution: Lattice currently does not offer an example flex cable solution to connect the Lattice Nanovesta sensor to the Lattice HDR-60 evaluation board. If you would like to design such a cable, the sensors will typically expect 50 ohm traces both ...
6963 - CertusPro-Nx: What are the recommended LPDDR4 trace impedance for CertusPro-NX devices?
Solution: There are three options presented: - 50-ohm single-ended with 100-ohm differential - 40-ohm single-ended with 80-ohm differential - 48-ohm single-ended with 96-ohm differential Here are some notes from our SME regarding the trace impedance ...
280 - Power Manager II: How many I2C loads can I put on an I2C chain for Power Manager II devices?
When using the Power Manager-II; POWR1220AT8, POWR1014A or POWR6AT6, it is important to know the loading and driving source of the full set-up. In a case where there are just a few I2C loads, whether Lattice POWR devices or others, the designer needs ...
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