6040 - CrossLink: What is the layout recommendation for LIA-MD6000-6KMG80E?
If we are referring to tables 3.1 and 3.2 in FPGA-TN-02024 (PCB Layout Recommendation document), we will use the same value for ctfBGA. In this case, 0.300 for SMD and 0.200 for NSMD. This is also reflected in Table 3.2
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5406 - Can Crosslink device layout be implemented without blind vias? Can I get an example for such layout?
You can find an example page 7 of the PCB Layout Recommendation for BGA Packages (FPGA-TN-02024) document. The example given has blind vias while the other 3 examples (which is found on pages 16, 17 and 47) are stacked vias. However, it also depends ...
6567 - Crosslink: What is the meaning of "aaa" characters in the Crosslink IBIS model?
Description: The "aaa" characters are unused for Crosslink devices but might be used for other devices (i.e., Crosslink-NX). These "aaa" characters are only added to comply with the 20 characters of the naming convention.
5915 - CrossLink: Where can I find documentation about Master Link board Rev D?
Please use documentation on CrossLink Rev C for your customers who are using Rev D. Generally, the change is just an improvement of the circuit layout on the board in order to remove the wire jumper that is present in Rev C and implement in Rev D. ...
2699 - The Lattice layout file is in Allegro .brd format, can Lattice translate the file to other formats?
Description:Lattice provides the Allegro .brd formatted layout file for the Lattice all evaluation boards. A designer would like to import the layout into another preferred PCB layout tool. Solution:The formal answer is no, in that PCB layout ...
5615 - Crosslink: Is the pin-out for the LIA-MD6000-81 identical to the pinout for the LIF-MD6000-csfBGA81? I can download the Excel pinouts for the 'LIF' Crosslink family, but I cannot find separate documentation for the Crosslink Automotive device.
For the pinout information of automotive parts, you may check FPGA-DS-02013, link: http://www.latticesemi.com/view_document?document_id=51753 They are of the same pinout information for LIF variants which is described in FPGA-DS-02007, link: ...