1674 - LatticeECP2/M: Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?

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• 1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?

  For generic FPGA input reference clock, DC coupling is what needs to be selected. The generic FPGA IO buffer architecture structure does not support AC coupling. Note: Dedicated SERDES reference clocks that have a CML buffer, can be AC or DC coupled. ...

• 1561 - LatticeECP3: Why are the LVDS input terminations modeled as resistors to 1.25v in the IBIS model file?

  The LatticeECP3 LVDS input terminations on die include a midpoint connection to the bank VTT pins on the device. This is why it is recommended in the LatticeECP3 data sheet to leave the bank VTT pins floating when using LVDS input terminations and to ...

• 852 - Should I add external series resistors to my parallel bus to improve the signal integrity?

  Description: A device is driving a large number of IOs that switch between VCCIO and GND in a parallel data bus. The designer knows that with an unterminated bus there can be reflections if the signal traces are too long which could decrease the ...

• 1636 - LatticeECP3: What is the recommended specifications to connect between Lattice Devices to Aptina HiSPi interface chip?

  If it’s to connect a sensor like the Nanovesta board close to the HDR-60, I’d recommend using flex cable, the metal layers are much the same work as laying out a PCB except the material used is now flexible mylar instead of FR4 material or others ...

• 2674 - PAC Designer: In Trim Configuration Options, what does "Open External Resistors(s) Threshold" imply?

  PAC designer software Trim Configuration utility calculates values of resistors connected between Power Manager and DC-DC converter for trimming the DC-DC conveter output. In Trim Configuration options the "open external resistor threshold" ...