6305 - MachXO: Where to find the automotive BSDL files?
The automotive BSDL files for MachXO should be the same functionality as the standard device files on the website.
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399 - Which Lattice devices have BSDL files available?
A BSDL (Boundary Scan Description Language) file is available for every Lattice device with a JTAG port. This file, standardized by the IEEE1149.1 specification, describes all information necessary to perform boundary scan testing. Included are ...
6445 - Can you generate an application specific BSDL file for a Lattice devices?
The Deployment tool can only generate the Application Specific BSDL file which support the FLASH block thus requiring the JEDEC file. Lattice devices that didn’t have the Flash has no Application Specific BSDL supported for the Deployment tool. The ...
2009 - MachXO:Which IBIS models should I use for the MachXO JTAG signal pins?
Solution: For the JTAG input pins, use the LVCMOS input models, input threshold voltage is referenced using the VCCAUX value, and select the model that has: TCK: bus keeper = NONE TDI: bus keeper = pull up TMS: bus keeper = pull up For the JTAG ...
5615 - Crosslink: Is the pin-out for the LIA-MD6000-81 identical to the pinout for the LIF-MD6000-csfBGA81? I can download the Excel pinouts for the 'LIF' Crosslink family, but I cannot find separate documentation for the Crosslink Automotive device.
For the pinout information of automotive parts, you may check FPGA-DS-02013, link: http://www.latticesemi.com/view_document?document_id=51753 They are of the same pinout information for LIF variants which is described in FPGA-DS-02007, link: ...
4572 - ECP3: Where to find component symbol for ALTIUM CAD tool associated to Lattice FPGA?
Lattice only provides OrCAD captured schematic symbols for Lattice FPGA's. Which user can find under respective FPGA product page, section Documentation > Technical Resources > Schematic symbols. ALTIUM CAD tool has an option for translating complete ...