2674 - PAC Designer: In Trim Configuration Options, what does "Open External Resistors(s) Threshold" imply?
PAC designer software Trim Configuration utility calculates values of resistors connected between Power Manager and DC-DC converter for trimming the DC-DC conveter output.
In Trim Configuration options the "open external resistor threshold" parameter, which is set by the user, determines the maximum value of resistor to be connected in the network. Beyond this value the Trim Calculator would consider the resistor to be open.
For eg: Setting values as 10,000 ohm, results in replacing calculated resistor values above 10,000 ohm with an open circuit. This parameter should be used to synthesize fewer resistors to be connected between the trim pin of the Power Manager and the DC-DC Converter.
Please refer to application note AN6074 for more details on interfacing the Trim Output of Power Manager Devices to DC-DC Converters.
Related Articles
852 - Should I add external series resistors to my parallel bus to improve the signal integrity?
Description: A device is driving a large number of IOs that switch between VCCIO and GND in a parallel data bus. The designer knows that with an unterminated bus there can be reflections if the signal traces are too long which could decrease the ...
Locating and Exporting Pin Package Lengths or Delay file (Trace_Length & Package_Delay)
Export the Pin Package Trace Lengths and Delay Files using Lattice Radiant Devices Covered: iCE40UP, Nexus, Nexus 2, Avant, MachXO4/XO4D Export the Pin Package Trace Lengths File using Lattice Diamond Devices Covered: MachXO/XO2/XO3/XO3D, CrossLink, ...
6176 - MachXO2/MachXO3: Why there is no JTAG external pullups (TDI,TDO,TMS) recommendation in our documents such Hardware Checklist and Programming and Configuration user guide while external pull-ups were added in our Lattice demo and evaluation boards.
MachXO2 and MachXO3L/LF TDI,TDO,TMS signals have internal pull-ups, so external pull-ups are not required. However, good engineering practice for a critical bus like JTAG is to augment the internal pull-ups with external if the bus will not always be ...
1561 - LatticeECP3: Why are the LVDS input terminations modeled as resistors to 1.25v in the IBIS model file?
The LatticeECP3 LVDS input terminations on die include a midpoint connection to the bank VTT pins on the device. This is why it is recommended in the LatticeECP3 data sheet to leave the bank VTT pins floating when using LVDS input terminations and to ...
1674 - LatticeECP2/M: Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?
Unlike LatticeECP3 and LatticeSC families which have programmable termination for LVDS IO, LatticeECP2/M family does not have an on chip termination resistor for FPGA IO in LVDS input mode.