1561 - LatticeECP3: Why are the LVDS input terminations modeled as resistors to 1.25v in the IBIS model file?
The LatticeECP3 LVDS input terminations on die include a midpoint connection to the bank VTT pins on the device. This is why it is recommended in the LatticeECP3 data sheet to leave the bank VTT pins floating when using LVDS input terminations and to not mix the use of LVDS input terminations with single ended type input terminations due to the potential for crosstalk through the floating bank VTT pins. The LatticeECP3 IBIS model uses an average common mode value for a true LVDS output (+1.25v) for the expected resultant bias of the floating VTT pin as a voltage source in the model. In the real devices, the bank VTT pins will float to the common mode level generated by the average of the LVDS outputs driving the LatticeECP3 LVDS inputs; If instead you need a fully isolated LVDS input termination that has no connection to the VTT pins, then disable the on die LVDS input termination and place an external 100 ohm resistor on the PCB physically close to the LVDS input BGA balls.