1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?

1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?

For generic FPGA input reference clock, DC coupling is what needs to be selected. The generic FPGA IO buffer architecture structure does not support AC coupling. Note: Dedicated SERDES reference clocks that have a CML buffer, can be AC or DC coupled. But these are not generic FPGA IO buffer. These rules apply to the  LatticeECP, Lattice ECP2/M, and LatticeECP3.