7335 - Is there an available 3d model for any Lattice FPGA Devices?

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  A BSDL (Boundary Scan Description Language) file is available for every Lattice device with a JTAG port. This file, standardized by the IEEE1149.1 specification, describes all information necessary to perform boundary scan testing. Included are ...

• 1779 - LatticeECP3: Does Lattice provide IBIS model for SERDES inputs and outputs of LatticeECP3?

  Currently Lattice does not provide LatticeECP3 IBIS model for SERDES input and outputs such as HDINP/N and HDOUTP/N. Alternatively, we recommended you use the LatticeECP3 HSPICE IO Kit to reach their simulation goals. The Lattice HSPICE IO Kit is ...

• 1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?

  For generic FPGA input reference clock, DC coupling is what needs to be selected. The generic FPGA IO buffer architecture structure does not support AC coupling. Note: Dedicated SERDES reference clocks that have a CML buffer, can be AC or DC coupled. ...

• 6445 - Can you generate an application specific BSDL file for a Lattice devices?

  The Deployment tool can only generate the Application Specific BSDL file which support the FLASH block thus requiring the JEDEC file. Lattice devices that didn’t have the Flash has no Application Specific BSDL supported for the Deployment tool. The ...

• 729 - IBIS Model: How do I find the output resistance of an I/O?

  An IBIS Model is a mapping of voltage to current values for a given I/O standard, slew rate, and drive strength. User can estimate the output resistance by using a simple slope formula, in relative to the flow of current. Using Ohm's law: Resistance ...