1779 - LatticeECP3: Does Lattice provide IBIS model for SERDES inputs and outputs of LatticeECP3?

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• 1911 - How can I generate a much smaller IBIS model file that only includes the IO types defined in my project?

  Situation: An IBIS model file from the Lattice web site includes all the programmable IO types a device can be set to, but the IBIS model file is very large and for some simulators, can slow the simulation setup time substantially. It is desired to ...

• 1756 - LatticeECP3: What IBIS models are needed to simulate the LatticeECP3 SERDES?

  For CML simulation of the SERDES inputs or outputs, we recommended to use the LatticeECP3 HSPICE IO Kit. These HSPICE models can be requested from our website under HSPICE I/O Kit Request page.

• 1561 - LatticeECP3: Why are the LVDS input terminations modeled as resistors to 1.25v in the IBIS model file?

  The LatticeECP3 LVDS input terminations on die include a midpoint connection to the bank VTT pins on the device. This is why it is recommended in the LatticeECP3 data sheet to leave the bank VTT pins floating when using LVDS input terminations and to ...

• 729 - IBIS Model: How do I find the output resistance of an I/O?

  An IBIS Model is a mapping of voltage to current values for a given I/O standard, slew rate, and drive strength. User can estimate the output resistance by using a simple slope formula, in relative to the flow of current. Using Ohm's law: Resistance ...

• 1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?

  For generic FPGA input reference clock, DC coupling is what needs to be selected. The generic FPGA IO buffer architecture structure does not support AC coupling. Note: Dedicated SERDES reference clocks that have a CML buffer, can be AC or DC coupled. ...