851 - Can I drive long PCB traces with an LVCMOS output?
Yes. When using the LVCMOS output settings with long 50 ohm PCB traces or cables, you will need to use the IO's higher output current settings and add an external 33 ohm series resistor for a good 50 ohm source termination with minimal ringing at the receiver. PCB traces are considered to be long when they are electrically longer in delay than the IO's output rise or fall time.
The reason for using the higher output current settings is that for a 50 ohm
source terminated output IO driving a 50 ohm PCB trace with no end termination
and a 3.3v VCCIO, that IO will need to source or sink current of value:
Required current = VCCIO/PCB_Z0/2 = 3.3v/50/2
Required current = 33 ma
That is the current necessary for both the pullup and pulldown transitions to "charge up" the long PCB trace. After the PCB trace is charged up to the fully switched level, the IO output current required becomes zero. Typically the IOs will be able to provide more output current than the IO current setting specified, so using a 16 or 20ma setting gives a fairly good result for a source terminated drive.
Do note that for long PCB traces, the switching current required would be much higher than 33ma without the added external series resistor. The added series resistor basically increases the output impedance of the IO such that it then better matches the PCB trace impedance, which then greatly reduces signal reflections along the trace, and of course, lowers the required IO current. The lower IO current also has the benefit of reducing bank SSO noise.
Also, if you set an output IO current too low, this can result in an inadequately switched signal edge at the receiver, often times seen as a "stairstep" waveform. The stairstep occurs due to the lower current IO setting not providing enough current to charge up the 50 ohm PCB trace in a single step, and instead taking multiple reflections to incrementally charge up the trace to the fully switched level. A stairstep edge can be a concern for clock signals due to the poorly defined edge transition. For data bits, a stairstep edge can be an issue if the delay of the long PCB trace is a significant portion of the clock period.
If you would like to reduce the IO output current required further, you can in addition to the series source termination, also add midpoint biased 50 ohm end terminations at the receivers, and this will reduce the current required to 1/2 that described above, because now the IO is switching +/- one half of the VCCIO voltage around the mid point bias level:
Required current = VCCIO/2/PCB_Z0/2 = 3.3v/2/50/2
Required current = 16.5 ma
When adding the midpoint biased end termination, the IO output current never goes to zero. The IO will either source or sink 16.5ma into the end termination depending on the IO output state.
Some receivers have built in on die terminations with a midpoint bias setting. If the receiver you're using does not have this feature, you can add external resistors or resistor packs near the receiver inputs to achieve a similar result. Typically this would consist of a resistor divider with 100 ohms to VCCIO and 100 ohms to GND with the center tap attached to the receiver input. An alternate method is to use 50 ohm terminations tied to a 1/2 VCCIO regulator voltage (often times this is called a "Vtt" supply).