1592 - How much duty cycle variation will a clock signal have at an output IO?

The answer to the amount of duty cycle variation a clock signal can have at an output IO depends on several factors:

Clock source characteristics (frequency, rise time, fall time, duty cycle, DC offset)
Use of the clock source within the device (PLL, DLL, routing using primary, edge, or general purpose)
Frequency of the output clock
Output IO type, current and slew settings
PCB loading

All of those items above can affect the output duty cycle. For characteristics within the device, it is recommended that you review the device datasheet for more information about the min and max duty cycle variation. For output IOs driving PCB traces, it is recommended to do an IBIS or HSPICE simulation to estimate the duty cycle variation for that IO at the current and slew rate setting.

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1592 - How much duty cycle variation will a clock signal have at an output IO?

1592 - How much duty cycle variation will a clock signal have at an output IO?

Related Articles

1911 - How can I generate a much smaller&nbsp;IBIS model file that only&nbsp;includes the IO types&nbsp;defined in my project?

851 - Can I drive long PCB traces with an LVCMOS output?

852 - Should I add external series resistors to my parallel bus to improve the signal integrity?

121 - How can I view the output IO waveform with IBIS model?

508 - Why can't I drive a long PCB trace with a low current setting and get good signal quality?

1911 - How can I generate a much smaller IBIS model file that only includes the IO types defined in my project?