Related Articles
1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?
For generic FPGA input reference clock, DC coupling is what needs to be selected. The generic FPGA IO buffer architecture structure does not support AC coupling. Note: Dedicated SERDES reference clocks that have a CML buffer, can be AC or DC coupled. ...
1674 - LatticeECP2/M: Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?
Unlike LatticeECP3 and LatticeSC families which have programmable termination for LVDS IO, LatticeECP2/M family does not have an on chip termination resistor for FPGA IO in LVDS input mode.
6084 - CrossLink-NX: Do we have adaptor to connect for MIPI DPHY Connector on CL-NX-Evaluation Board?
We do not have adaptor to connect J6 header. Also MIPI interface through J6 has not tested. However, by looking at the datasheet of the header pin, Wurth part number: 61302021121 (url: ...
1636 - LatticeECP3: What is the recommended specifications to connect between Lattice Devices to Aptina HiSPi interface chip?
If it’s to connect a sensor like the Nanovesta board close to the HDR-60, I’d recommend using flex cable, the metal layers are much the same work as laying out a PCB except the material used is now flexible mylar instead of FR4 material or others ...
729 - IBIS Model: How do I find the output resistance of an I/O?
An IBIS Model is a mapping of voltage to current values for a given I/O standard, slew rate, and drive strength. User can estimate the output resistance by using a simple slope formula, in relative to the flow of current. Using Ohm's law: Resistance ...