4076 - ECP5: While migrating device pinout from LatticeECP5-25 to LatticeECP5-85 device, how to handle the pins when some pins are notified as NC in LatticeECP5-25 and GND or RESERVED in LatticeECP5-85 device?
When migrating the device pinout from LatticeECP5-25 to LatticeECP5-85 devices, generally, the NC pins in LatticeECP5-25 pinout can be notified as GND or RESERVED pins in LatticeECP5-85.
If the LatticeECP5-85 pins are notified as GND, then you can connect the NC pins to GND. Whereas, if they are notified as RESERVED, then the pins can be left floating (not connected on board).
Related Articles
157 - I am migrating from LatticeECP3 device/package to another LatticeECP3 device/package. Is there a description of the differences between the various devices and packages?
LatticeECP3 pinout and migration files can be found on the LatticeECP3 Web Page. On the left side of the window, select Data Sheets You will see a list of the most current versions of the following: LatticeECP3 Data sheet & Errata Pinout (.csv) files ...
6290 - MachXO2: For NC Pins, Is it mandatory for them to have NO Connections?
NC pins can be tied to VCC, ground, left floating or used to bridge since they are not connected internally.
738 - How should user connect unused I/O pins in a Lattice device?
I/O pins which are unused in a design typically do not need to be grounded or connected anywhere. Some of the devices have global setting for pull-ups on I/O likes -Up, -Down or Bus-Hold, and others may have settings for each pin. By default, Lattice ...
5615 - Crosslink: Is the pin-out for the LIA-MD6000-81 identical to the pinout for the LIF-MD6000-csfBGA81? I can download the Excel pinouts for the 'LIF' Crosslink family, but I cannot find separate documentation for the Crosslink Automotive device.
For the pinout information of automotive parts, you may check FPGA-DS-02013, link: http://www.latticesemi.com/view_document?document_id=51753 They are of the same pinout information for LIF variants which is described in FPGA-DS-02007, link: ...
1673 - LatticeECP/LatticeECP2/M/LatticeECP3: What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?
For generic FPGA input reference clock, DC coupling is what needs to be selected. The generic FPGA IO buffer architecture structure does not support AC coupling. Note: Dedicated SERDES reference clocks that have a CML buffer, can be AC or DC coupled. ...