6290 - MachXO2: For NC Pins, Is it mandatory for them to have NO Connections?
NC pins can be tied to VCC, ground, left floating or used to bridge since they are not connected internally.
Related Articles
2009 - MachXO:Which IBIS models should I use for the MachXO JTAG signal pins?
Solution: For the JTAG input pins, use the LVCMOS input models, input threshold voltage is referenced using the VCCAUX value, and select the model that has: TCK: bus keeper = NONE TDI: bus keeper = pull up TMS: bus keeper = pull up For the JTAG ...
4076 - ECP5: While migrating device pinout from LatticeECP5-25 to LatticeECP5-85 device, how to handle the pins when some pins are notified as NC in LatticeECP5-25 and GND or RESERVED in LatticeECP5-85 device?
When migrating the device pinout from LatticeECP5-25 to LatticeECP5-85 devices, generally, the NC pins in LatticeECP5-25 pinout can be notified as GND or RESERVED pins in LatticeECP5-85. If the LatticeECP5-85 pins are notified as GND, then you can ...
6305 - MachXO: Where to find the automotive BSDL files?
The automotive BSDL files for MachXO should be the same functionality as the standard device files on the website.
730 - MachXO: Why do external pull up required for MachXO SLEEPN pin?
The SLEEPN pin on the MachXO device is a control signal for the internal regulator. If the pin is pulled low it puts the device into a low power state. Although the SLEEPN pin has a weak internal pull-up, an external pull-up is recommended if the pin ...
1320 - LatticeXP2: Which voltage rail should CFG and TOE pins be pulled up to?
The LatticeXP2 CFG[1:0] and TOE pins are internally linked to the VCC core voltage and can be pulled up to either VCC core or 3.3v. For more information about LatticeXP2 TOE and CFG[1:0] pins, , please refer to LatticeXP2 Family Data Sheet.