1320 - LatticeXP2: Which voltage rail should CFG and TOE pins be pulled up to?
The LatticeXP2 CFG[1:0] and TOE pins are internally linked to the VCC core voltage and can be pulled up to either VCC core or 3.3v.
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2655 - Platform Manager 2: Is there a low cost way to power the ProcessorPM-POWR605 off of a 5V rail?
Depending on the nature of the 5V rail, the ProcessorPM-POWR605 can be powered using a simple voltage divider. This very low cost solution uses a stable 5V supply with an attenuator circuit. The 3.3V rail is developed from a voltage divider using 120 ...
1983 - Should I add a ferrite bead to the VCC core voltage supply?
No, you do not need to add a ferrite bead between your VCC regulator output and the VCC pins on the FPGA. There are two reasons for not adding the ferrite bead, the first being that the VCC pins are less susceptible to power supply noise so they do ...
176 - In IBIS models, the drive high, or "[pullup]" section lists strange voltage ranges and appears to be inverted. Why is this?
The IBIS specification uses voltages relative to ground for drive-low (pulldown), but voltages relative to the appropriate supply rail for drive-high (pullup). To convert to ground-relative voltages, take the nominal I/O supply voltage and subtract ...
2009 - MachXO:Which IBIS models should I use for the MachXO JTAG signal pins?
Solution: For the JTAG input pins, use the LVCMOS input models, input threshold voltage is referenced using the VCCAUX value, and select the model that has: TCK: bus keeper = NONE TDI: bus keeper = pull up TMS: bus keeper = pull up For the JTAG ...
2855 - Power Manager II: Do I need to connect a 100 ohm series resistor between monitored voltages and VMON pins on the POWR1220AT8 device?
No, you can connect the VMON pins directly to monitored voltages which are between 0 and 5.9V. Some of the Lattice evaluation board schematics do include a resistor between the monitored voltage and the VMON pins. This is typically only used with the ...