Description:

A new board design has been operating correctly during initial testing, the FPGA design was changed to add the full feature set and now the new design begins to fail after a short amount of time. What could cause this?

Solution:

Have you added a time locked IP into the design? If so, this might be the cause.

It could also be power supply related. Check the board power supply voltages with a DVM, both with the FPGA un-programmed, and then again with the full feature set implemented and operating. Compare the before and after supply voltages. If you see a significant voltage drop for power supplies at the FPGA pins, then it is likely that either the regulators do not provide enough current, or they are beginning to thermally shut down, or the power supply planes to the FPGA, are not wide enough, or thick enough copper to maintain the supply voltage to the FPGA with the larger currents your full feature design might require.

Given that LC filtering is often applied to power supplies and the likelihood that multiple supply regulators may be cascaded, it is probably a good idea to use an oscilloscope to probe the individual power supply voltages and look for ringing or drooping responses at each voltage regulator input and output pin. The full feature design might be drawing repetitive supply currents that incite a low frequency LC resonance, the oscilloscope will be able to show if this is occurring.