Device Constraint Editor
7688 - [All Nexus] Why Lattice Radiant tool shows Error <71241012> The clock port [clock_name] is assigned to a non-clock pin ?
This error appears when you are assigning a clock port to a non-clock pin. To resolve this, you can force Radiant tool to use this attribute in the .pdc file: ldc_set_attribute {USE_PRIMARY=FALSE} [get_nets {clock_name}_c] Example: ldc_set_attribute ...
5497 - All Devices: Can the USERCODE be defined using an HDL attribute in RTL?
No, the USERCODE attribute is not supported through HDL attributes. Users have to use the Device Constraint Editor in Radiant or Spreadsheet View in Diamond to assign USERCODE.
2350 - All FPGAs: I have successfully run Place & Route Design with the Commercial device. How can I generate a trace report for the same device with Industrial grade and 85C but without re-running the synthesis and MPAR?
Description: You can change the post-route preference file (.prf) by adding "INDUSTRIAL;" and "TEMPERATURE 85C;". Also at the same time the trace options can be updated in ispLEVER's Tools-> Trace Options or Lattice Diamond's Strategies->Place & ...
1099 - Lattice Diamond: I/O: How to create a FPGA pinout that will work on the board?
Lattice Diamond: I/O: In modern FPGA designs there are plenty of design constraints in selecting and designing to a FPGA pinout. There are I/O Banks, Edge Clocks, PLLs, DLLs, VREFs, DQS Lanes etc. which must all be managed and drive the selection ...
6858 - MachXO Family: How to make your own Schematic Symbol in Diamond?
See below steps as an example: 1) Code the logic of your Asynchronous Set and Reset on to a .v file (Note: make sure your .sch is excluded first in the implementation as shown)
5303 - ispMACH4000: How to define "block-level initialization term" in Verilog?
Once the design is loaded in ispLever Classic, open the Constraint editor. In the Constraint Editor, after scrolling to the far right, there are options to select the Register powerup value (either SET or RESET or NONE). This will initialize the ...
2243 - LatticeECP3: How can I get around the error "trace: Mangled ncd file before signal read"?
Description: Lattice Diamond Timing Analysis tool (trace) outputs this error when it encountered NCD file that failed integrity check. Typically this is due to the file being corrupted. You can get around this issue by removing the NCD file and ...
6694 - Nexus: Why the JTAG_PORT/SLAVE_SPI_PORT pins are not usable as GPIO in USERMODE in Nexus Device Family?
This is a known issue for Nexus Devices and will be fixed as soon as possible for the meantime to use JTAG_PORT/SLAVE_SPI_PORT ports in user mode as GPIO please enable SLAVE_I2C/I3C_PORT to proceed; the downside we are preserving the IOs as SDA and ...
6268 - Radiant: Does Radiant has linter?
Description: We do not have a linter feature on Radiant. The RTL code is checked by the software when either updated or has been inserted in the project and then gives the appropriate message result (info/warning/error) on the output window. ...
1871 - LatticeXP2: Can the PROGRAMn and DONE pins be used as general purpose input/output?
The PROGRAMn and DONE pins on the LatticeXP2 can be either dedicated for device configuration, or they can become General Purpose I/O (GPIO). The CFG0 input pin to the FPGA controls how these pins behave. You can find full details in LatticeXP2 ...
1778 - MachXO2: Can I really use the PROGRAMN pin for user i/o without disrupting the ability to program a blank device in-system?
On the MachXO2 device, PROGRAMN is a dual use pin. Our technote TN1204 "MachXO2 Programming and Configuration Usage Guide" describes the behavior of PROGRAMN and other sysCONFIG pins (e.g. INIT, DONE) in detail. At issue here is that for an erased ...
5742 - Radiant: How to export the pinout file?
Radiant Software can export a pinout/pin-layout file in CSV format. When the Device Constraint Editor is open, go to File > Export.
2378 - Diamond: In Lattice Diamond, what is the difference between a Pin Layout File and a Pin Out file?
A Pin Layout File is a report of pin information and assignments in your design. It is created from within the Lattice Diamond Spreadsheet View using File>Export Pin Layout File The Pin Layout File can be a list of available pins, pad names, ...
2351 - All FPGAs: How do I check the timing of the paths across two clock domains in the trace report?
Description: If the two clocks (clock1_c and clock2_c) have an obvious timing relationship in the design, the timing information for paths across the two clock domains will be shown in the trace report as long as you have added associated timing ...
6440 - Device Constraint Editor: How to choose the D-PHY location for Crosslink-NX?
Description: To set the location of the desired HARD DPHY module via Radiant, do the following procedures: (1) Create a top module either using verilog or vhdl source code. (2) Under the top module, insert the synthesis loc = DPHY1 inside the ...
6821 - Lattice Diamond: How do I change the TCK value of Reveal?
1) Opening Reveal Analyzer and Clicking Design > Cable Connection Manager
6819 - Lattice Diamond: How do i generate the pin layout files in Diamond?
You can generate the pinout file for the desired device through the diamond SW. Please follow the steps below: 1) Open Spread Sheet View
7227 - Radiant and Diamond: How do you view or print a waveform with ModelSim/Questa using the VCD file generated by Reveal Analyzer?
Description: The VCD (Value change dump) file is an ASCII file defined by IEEE 1364. It can be generated by a Verilog command or system function which can be used as the stimulus to the testbench and record variations of waveform. Here are the steps ...
7161 - Radiant: How are multiple lines of constraints handled in the device constraint editor?
Description: When handling multiple constraint commands in a constraint files, there might be confusion in which settings are applied. This FAQ will give examples on how device constraint editor handles it. See examples below for ldc_set_sysconfig ...
6181 - All Nexus / Device Constraint Editor: How can the user set the DONE, INITN, and PROGRAMN pins of Nexus devices as GPIO during user mode?
Users need to program the feature row with the .fea file generated during the design flow (Note: If changes are made on the Global settings, user needs to rerun the design flow to re-generate a new .fea file that reflects the changes on the Global ...
7082 - ispLever Classic 2.1: How to resolve the issue when the text editor in ispLever Classic appears in the taskbar but the window cannot be opened?
Workaround 1: Press and hold the Shift key, then right-click the stuck text editor icon in the taskbar then click Maximize Workaround 2: You can change the text editor to your own desired text editor as a workaround. To do this: 1. Open ispLever ...
6097 - Lattice Diamond: How to change I/O attributes on JTAG pins?
Set JTAG_PORT to DISABLE in the software so that the I/O becomes GPIO. The user could then change the I/O attributes on that shared pin. The JTAGEN pin will not control the IO standard and drive strength setting of the IO. If the JTAG is not ...
6564 - Radiant and All Nexus: How to reserve certain pin or pins without any logic in the design?
Description: In planning for a design, ports and pins are should be set earlier prior to adding logic in the design, and reserving a pins without any logic is part of that hardware abstraction. Solution: Procedure to reserved certain pin or pins. 1. ...
6492 - Lattice Radiant and Diamond: How do i resolve core0 error when Running reveal analyzer? How to resolve Error "Core0 incorrect pattern readout" while running Reveal Analyzer?
Description: When running the reveal analyzer a "Core0 incorrect pattern readout" error is encountered causing the tool to not generate its desired waveforms. Solution: This can be resolved by making sure that you have the following: 1) JTAG TCK is ...
6485 - Lattice Radiant: What is Glitchfilter in Device constraint editor?
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.