1099 - Lattice Diamond: I/O: How to create a FPGA pinout that will work on the board? <br>
Lattice Diamond: I/O: In modern FPGA designs there are plenty of design constraints in selecting and designing to a FPGA pinout. There are I/O Banks, Edge Clocks, PLLs, DLLs, VREFs, DQS Lanes etc. which must all be managed and drive the selection process. In order to guarantee that a selected pinout will work on the board and in the FPGA the FPGA designer really must finish the design before the pinout can be nailed down.
The Lattice Diamond software provides a better way. Using the I/O Assistant implementation strategy the FPGA designer can simply define the IO structure without having to code the full details of the FPGA design. The I/O Assistant flow takes RTL from the user and runs only the necessary underlying tools to create a PAD report file which shows the Bank voltages, Pins and I/O types. The internal modules can be left as hanging nets or undriven inputs. Using this flow the FPGA designer can quickly provide a pinout to the board designer with confidence that it will work in the complete design.
For more information on the I/O Assistant flow see the Lattice Diamond User Guide.