2351 - All FPGAs: How do I check the timing of the paths across two clock domains in the trace report?

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• 212 - Diamond: Why do users have preference items in the trace report with 0 timing score?

  There are several reasons why users will see this happen: The timing constraint specified is covered by another timing constraint in the preference file. This is most often seen when the design has two related clocks. Trace will provide timing ...

• 940 - Diamond: Timing: Why are there two trace reports in the Lattice software?

  Diamond: Timing: There are two trace reports (a Map trace report and a Place-and-Route (PAR) trace report) that serve two different purposes. The Map Trace report has estimated routing. It should be used to verify the paths you expect are being ...

• 2592 - What does "potential circuit loops found in timing analysis" in trace report mean?

  Solution: The use of combinational loops has long been discouraged because this can cause significant stability and reliability problems in a design. The combinational loop behavior is usually dependent on the relative propagation delays of the ...

• 129 - Lattice Diamond: How can I single out a specific path or transfer in the timing analysis TRACE report?

  TRACE lists the paths per timing preference starting from the worst case path going down. Let's say you want to look at a path that maybe the 1001st worst case path in the design. You do not want to list 1001 paths in the trace report. How can this ...

• 2633 - How to use PAR_ADJ with FREQUENCY and set the ratio between the clock domains? 

  PAR_ADJ allows you to loosen requirements for PAR results while tightening up the requirements reported by the timing analysis tool. The variance in required timing values on PAR and TRACE enables you to experiment more efficiently with the strategy ...