Quality & Reliability
7658 - Quality / Reliability : What is the manufacturing constant for calculating the MTBF of CDC?
Tau for calculating MTBF Metastability is equivalent to 1.0003E-10 for SS models @ -40C and low VCC while Tau improves to 4.1929E-11* for TT models.
7071 - All Devices: What exactly does "Storage Temperature (Ambient)" mean?
Description: Please see the following points for clarification: Storage Temperature - temperature of the device when the power is OFF Ambient Temperature - temperature of the surroundings Operating Temperature - temperature of the device when the ...
6496 - Mach-NX, CertusPro-NX: Where can I learn more about the 2D Barcode/QR Code top marking on Lattice FPGA lid?
You can find the related document on this Lattice website link: https://www.latticesemi.com/view_document?document_id=53624
3612 - LatticeECP3: Is Lattice ECP3 device PCISIG (Peripheral Component Interconnect Special Interest Group) compliant in terms of Differential peak-to-peak input voltage (VRX-DIFF_P-P)?
Our Lattice ECP3 device is PCISIG compliant and passed PCISIG compliance tests at PCISIG workshop. The PCI Express Electrical and Timing Characteristics of our ECP3 datasheet says that the minimum value for Differential peak-to-peak input voltage ...
1105 - What is the moisture sensitivity level (MSL) of Lattice devices?
All Lattice through-hole mount devices are 28-pins or fewer and have an MSL of 1. For surface mount devices, please refer to respective package MSL in FPGA-TN-02041 - Solder Reflow Guide for Surface Mount Devices.
1072 - What is the solder reflow condition for Lattice DIP device package?
Lattice provides soldering guide for surface mount device in FPGA-TN-02041. PDIP packages are not surface mounted device thus it is not subjected to JEDEC reflow conditions. User should refer to standard wave soldering process for PDIP devices. The ...
3553 - Will it be possible to provide the RoHS Conversion date for a given Lattice part?
We don’t have RoHS conversion dates. None of our devices were converted to RoHS. Our RoHS-compliant (Pb-free) parts were compliant upon initial release
922 - What is the composition of Lattice device pin?
Lattice device material content and related RoHS information is available at: https://www.latticesemi.com/Support/QualityAndReliability https://www.latticesemi.com/en/Support/QualityAndReliability/DeviceMaterialContent.aspx
921 - How to determine lead free package option for Lattice FPGA device?
Please refer to Environmental Information section for RoHS related information. https://www.latticesemi.com/en/Support/QualityAndReliability For lead free part numbers refer to the ordering section of the datasheet but typically the "N" denotes lead ...
918 - What is the FIT rate for Lattice device?
FIT rate for Lattice device in included in Reliability report which consists of other test result. https://www.latticesemi.com/Support/QualityAndReliability Failure rates in this reliability report are expressed in FITS. Due to the very low failure ...
6024 - ECP2: About the Metastability of ECP2M and the latest FPGA
Definition: Metastability is no more an issue with newer devices after LC4128C-27T100C because it demonstrates smaller tr (resolution time) for 10 year MTBF.
801 - Power Manager II: What is the Peak Reflow Temperature for the ProcessorPM or POWR605?
Please refer to FPGA-TN-02041 - Solder Reflow Guide for Surface Mount Devices for more details. The ProcessorPM and POWR605 are the same device with QFNS 24 package type. User may refer to Table 8.2. Peak Reflow Temperature (TP) by Package Type and ...
6019 - Where to request a Statement/Letter of Volatility?
Description: For Statement/Letter of Volatility request, you may contact custreq@latticesemi.com.
800 - Power Manager II: What is the maximum junction temperature Tj for the POWR1220AT8 device?
The absolute maximum junction temperature of the PAC-POWR1208P1 is at 130°C. Operation at or above this temperature will permanently degrade performance or permanently damage the device. In addition, operation outside of the recommended operation ...
2143 - Where can I find MSL (Moisture Sensitivity Level) for various packages of Lattice devices?
Please refer to the FPGA-TN-02041 (Solder Reflow Guide for Surface Mount Devices) for the Solder reflow and rework process for Lattice surface mount products. The downloadable link of the document can be found here: ...
660 - Where can I find the Mean time between failures (MTBF) for a device?
Mean time between failures (MTBF) is the predicted elapsed time between inherent failures of a system during operation. Due to the very low failure rate of integrated circuits, it is convenient to refer to failures in a population during a period of ...
7304 - iCE40: Where can I find NVCM/Data Retention information for ICE40 UltraPlus device family?
Description: The ICE Ultra Plus device is a member of the ICE family which uses a common NVCM technology which is reported in the referenced qualification report. The qualification and reliability stress data applies to all devices in the ICE family. ...
5947 - Platform Manager 2 & L-ASC10: How to calculate the recommended maximum junction temperature for L-ASC10?
Use the formula: TJ = TA + Power * 0JA Where TJ and TA are the junction and ambient temperatures, respectively, and P is the power. 0JA is the effective thermal impedance between the die and its environment
6269 - Power Manager II: What is the Power Manager II's life status?
Estimates point out that these devices could remain in production for up to 10+ years. Kindly note that the years indicated are only estimates. Although we do not guarantee the longevity of our products, these are the estimates that we see that our ...
493 - Where can I find information about the Parameterized Module Instantiation (PMI) feature?
You can find information about the Parameterized Module Instantiation (PMI) feature in ipsLEVER or Lattice Diamond by invoking online Help and searching for PMI or Parameterized Module. In the online Help, you can also select the Contents tab. Expand ...
2089 - Do Lattice devices contain any Rare Earth materials as mandated by the US Department of Commerce National Security Assessment?
Solution: As per the US Department of Commerce National Security Assessment, it is mandatory that the following rare earth materials should not be used in any equipment related to security/defense. Neodymium, Dysprosium, Yttrium, Europium, Terbium, ...
420 - Which Lattice devices contain Beryllium?
Lattice has provided our customers with 2 documents that describe what materials are used in our devices. The first is the "Package Device Material Breakdowns" document which shows the breakdown by weight of the various different substances contained ...
364 - What does it mean when I have a part that is "dual-marked"?
The part number stamped on the top of some Lattice semiconductor parts is different from the part number listed in the data sheet. In fact, the one stamped on the part looks like a combination of 2 part numbers in the data sheet. Lattice defines such ...
1545 - Where can I find Quality and Reliability report for a Lattice device?
All reports regarding Quality and Reliability can be found on Lattice Smiconductors website, please follow the link Quality and Reliability Reports. One can find Product Family Qualification Summaries for various devices,which describes quality and ...
6174 - How to request for any Product Family Qualification Summary?
Kindly send an email to custreq@latticesemi.com for the request of any Product Family Qualification Summary.
2547 - ispPAC-POWR1014/A: Where can I find information about the package thermal resistance of the ispPAC-POWR1014/A device?
Solution:The Lattice Thermal Management document provides these details and can be found here: Thermal Management Pg. 3 gives the package data for the TQFP 48, 1.4mm thick (applicable package for the POWR1014/A) for Package Thermal Resistance ...
5778 - Is Cobalt Reporting Template (CRT) emergency found in Lattice products?
Lattice does not use Cobalt in any of its products.
5772 - Where can I find the Package Thermal Resistance value of a legacy device or a device that is not specified on the Thermal Management Technical Note (FPGA-TN-02044)?
If not specified on the "Device/Package Thermal Resistance" section you can refer to the generic table, Table 3.1. Package Thermal Resistance. This section specifies the generic thermal resistance for legacy Generic Array Logic (GAL), CPLD, FPGA and ...
1969 - MachXO2: Does Lattice provide any test data for MachXO2 device subjected to atmospheric neutrons ?
The Reliability report for the MachXO2 Product Family has data on Soft Error Rate (SER) testing. SER testing is conducted to characterize the sensitivity of SRAM storage and device logic elements to High Energy Neutron and Alpha Particle radiation. ...
3745 - ispMACH 4000: What is the SER (Soft Error Rate) in ispMACH4000 devices? Is the SER data for neutron testing normalized to the published neutron flux rate for New York City at sea level?
SER is provided for the sensitivity of EECPLD storage and device registered logic elements to High Energy Neutron and Alpha Particle radiation as per JEDEC JESD-89. Stress / Structure REGISTERED LOGIC EECLPD Neutron 0.6 0 Alpha N/A 0 SER is measured ...
6099 - Platform Manager II: What is the lifespan of EEPROM (Memory Programming / Erase Specifications)?
Description: The L-ASC10 device is built at our Foundry partners United Microelectronics Corp. (UMC) in Taiwan and Seiko-Epson in Japan, on the Lattice EE8A Technology. The EE8A Technology demonstrates excellent data retention characteristics. ...