921 - How to determine lead free package option for Lattice FPGA device?

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• 1072 - What is the solder reflow condition for Lattice DIP device package?

  Lattice provides soldering guide for surface mount device in FPGA-TN-02041. PDIP packages are not surface mounted device thus it is not subjected to JEDEC reflow conditions. User should refer to standard wave soldering process for PDIP devices. The ...

• 582 - How can I determine if I have an authentic Lattice device?

  To ensure you receive authentic Lattice device always purchase through one of our Lattice Sales office or approved distributors. To find the office closest to you check out: Lattice Sales Office

• 5772 - Where can I find the Package Thermal Resistance value of a legacy device or a device that is not specified on the Thermal Management Technical Note (FPGA-TN-02044)?

  If not specified on the "Device/Package Thermal Resistance" section you can refer to the generic table, Table 3.1. Package Thermal Resistance. This section specifies the generic thermal resistance for legacy Generic Array Logic (GAL), CPLD, FPGA and ...

• 420 - Which Lattice devices contain Beryllium?

  Lattice has provided our customers with 2 documents that describe what materials are used in our devices. The first is the "Package Device Material Breakdowns" document which shows the breakdown by weight of the various different substances contained ...

• 2547 - ispPAC-POWR1014/A: Where can I find information about the package thermal resistance of the ispPAC-POWR1014/A device?

  Solution:The Lattice Thermal Management document provides these details and can be found here: Thermal Management Pg. 3 gives the package data for the TQFP 48, 1.4mm thick (applicable package for the POWR1014/A) for Package Thermal Resistance ...