Aldec (Third-Party Support)
6123 - Simulation tool: Does Lattice still provide license for Aldec Active-HDL?
Description: Our contract with Aldec has ended and we no longer support Active HDL licensing. In 2020, we have sent out a notification to existing ActiveHDL users about our migration to Mentor’s ModelSim simulator tool. We sincerely apologize if you ...
5863 - Why are virtual groups not restored when restarting a simulation and reloading the .awc file when creating virtual groups in the accelerated waveform window and saving to the .awc file?
It was observed that there is a warning message that it cannot display signals from the waveform file (.awc). The file does not match the associated simulation database (ASDB). If there are mismatching signals between the AWC and the ASDB file, this ...
5803 - Aldec error during Post-Route Gate-Level-Timing Simulation: "SDF: Error: *_vho.sdf(19): Instance /*_tb/slice_0i not found\"
Description: In the Aldec Simulator, an SDF error can be encountered. For example, # SDF: Error: *_vho.sdf(19): Instance /*_tb/slice_0i not found\. Solution: The error is mainly in the user's testbench file, not in the generated .vho and .sdf files. ...
5726 - Active-HDL: How to disable VITAL Glitch warnings?
This type of warning is generated during timing simulation, after Place and Route (PAR). The warnings are triggered due to the difference in propagation delay of two or more input signals to a logic gate. For example, consider a two-input AND gate ...
5399 - Aldec Simulation: No MIPI data after executing the run simulation and #KERNEL errors occur
Description: When using the Aldec Simulator, the following errors can occur when simulating MIPI. #KERNEL: ERROR : Fff: Clock after input divider is out of range #KERNEL: ERROR : Fvcout: Clock before output divider is out of range #KERNEL: ERROR : ...
3981 - Active-HDL: How to resolve unknowns (X) in timing simulation when the RTL simulation is fine and all constraints are met in Place and Route TRACE?
For post-route timing simulation, please set the SDF (Standard Delay Format) value and load as Maximal and Yes, respectively, in Aldec design settings. i.e. Step 1: In Aldec Active-HDL, select "Settings" from the Design menu. The Design Settings ...
3838 - Active-HDL: Warning: KERNEL_0085 "/ir_iic_tb/ir_inst/ir_rcv_0/rcv_data" does not have read access. Use switch +access +r for this region.
Description: The warning is generated by Active-HDL when some of the signals cannot be displayed in the waveform. Solution: To resolve this issue, and get internal signal visibility, set the read access to internal signals through GUI or script. ...
1200 - Simulation: ALDEC Active-HDL: How can I recompile my testbench without restarting Active-HDL from ispLEVER tool?
Simulation: ALDEC Active-HDL: For convenience, users may want to make changes to a testbench without exiting Active-HDL. To do this will require the recompiling of the testbench, and restarting the simulation. The simplest way to recompile the ...
1199 - Simulation: ALDEC Active-HDL: What Active-HDL commands can I issue from the command line?
Simulation: ALDEC Active-HDL: You can see the commands that can be issued from the command line by starting Active-HDL, then: Help -> On-line Documentation. Select the 'Contents' tab. Expand 'Active-HDL Help'. Expand 'Active-HDL Macro Language' This ...
1198 - Simulation: ALDEC Active-HDL: Why can't Active-HDL find the PCS *.txt file after a restart? ECP2M simulations doesn't work after the initial simulation.
Simulation: ALDEC Active-HDL: If a user tries to run functional simulations after a restart command in the Active-HDL console, the following error might occur: # EXECUTION:: ERROR : Auto configuration file for PCS module not found. PCS internal ...
1196 - Simulation: ALDEC Active-HDL: How to show signal hierarchy in the Active-HDL Waveform Editor? (I want to see the design hierarchy of a given signal.)
Simulation: ALDEC Active-HDL: To see the design hierarchy for a given signal do the following: 1. Invoke the Active-HDL Waveform Editor. 2. Move your mouse over to the column header at the top of the Waveform Editor (e.g. "Name", "Value", etc). 3. ...
1195 - ALDEC Active-HDL: Simulation: How can I make the ALDEC Active-HDL Waveform Viewer zoom in enough to see the details of my simulation?
ALDEC Active-HDL: Simulation: If an Active-HDL Waveform Viewer/Editor won't zoom in enough, the problem is probably in the resolution of the simulation. You check this by selecting from the Active-HDL toolbar Design -> Settings -> Simulation. Look ...
1053 - Aldec: How can user check if the license for Aldec Active-HDL is available?
Firstly, check the license file, make sure it contains ACTIVEHDL_LIC_NUMBER ALDEC and ACTIVEHDL_LATTICE_MIX_LT features. Then check the LM_LICENSE_FILE environment varible set up. The ispLEVER provides a tool (\ispCPLD\bin\lmtools.exe) to diagnose LM ...
115 - Active-HDL error: "ELAB2_0093" in mixed Verilog/VHDL design
Description: This happens when your top-level design is in VHDL but one of the lower-level modules (for example, PLL generated using IP Express) is in Verilog. Solution: Take note that Lattice OEM Compiled libraries have different nomenclatures for ...
114 - Active HDL: hanging after loading waveforms
Description: This can sometimes happen if you have the same variable being used in different loops. Solution: In the example below, it is recommended that you define a new integer variable for the second always block and the simulator will not hang ...
113 - Active-HDL: How to invoke and use in batch mode?
For running Active-HDL Lattice Edition in batch mode, execute "vsimsa" command from the DOS command window. Note that "vsimsa" does not have a graphical user interface (GUI). It is useful for running automated scripts or regression tests and it can ...
112 - Active-HDL: How to invoke and use in GUI Mode?
For running Active-HDL Lattice Edition stand-alone GUI, execute the command "avhdl" from the DOS command window. The following is an example macro file for simulating a Verilog design. The "avhdl" commands are compatible with ModelSim with some minor ...
110 - Aldec Active-HDL: Why do the simulation database and simulation results fail to refresh automatically?
By default, the simulation database and results displayed in the Waveform window do not refresh automatically. Changes to the simulation database are available only after a simulation step is finished or the simulation is stopped. This means that the ...