113 - Active-HDL: How to invoke and use in batch mode?
For running Active-HDL Lattice Edition in batch mode, execute "vsimsa" command from the DOS command window. Note that "vsimsa" does not have a graphical user interface (GUI). It is useful for running automated scripts or regression tests and it can be invoked as "vsimsa -do macro" from the command window.
The following is an example macro file for simulating a Verilog design. As "vsimsa" commands are compatible with Modelsim, converting existing Modelsim macros to Active-HDL macros is straight forward as shown below:
vlib work
vlog -v2k -work ./work file1.v file2.v file3.v top.v
vsim work.top -L ovi_ecp2 -PL pmi_work
In the macro file above, file1.v, file2.v, file3.v and top.v are the design files. The top.v file is the top-level design. The example assumes that the user is targeting the LatticeECP2 family. The "ovi_ecp2" library is the pre-compiled Verilog library for Lattice ECP2. The other pre-compiled FPGA Verilog libraries for other Lattice families are:
ovi_sc
ovi_ec
ovi_xp
ovi_ecp
ovi_machxo
ovi_xp2
The following is an example macro file for simulating a VHDL design.
vlib work
vcom -work ./work file1.vhd file2.vhd file3.vhd top.vhd
vsim work.top -L ecp2 -PL pmi_work
The other pre-compiled FPGA VHDL libraries for other Lattice families are:
sc
ec
xp
ecp
ecp2
machxo
xp2